PIC18F43K20-E/MV Microchip Technology, PIC18F43K20-E/MV Datasheet - Page 147

• Manufacturer Part Number: PIC18F43K20-E/MV
• Description: 8KB, Flash, 768bytes-RAM, 36I/O, 8-bit Family,nanowatt XLP 40 UQFN 5x5x0.5mm TUB
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F43K20-E/MV

• Processor Series: PIC18
• Core: PIC18F
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Data Ram Size: 512 B
• Interface Type: I2C, SPI, SCI, USB, MSSP, RJ11
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: UQFN-40
• Development Tools By Supplier: MPLAB Integrated Development Environment
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 125 C
• Supply Current (max): 30 uA
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / Rohs Status: Details

11.3
In Compare mode, the 16-bit CCPRx register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCPx pin
can be:
• driven high
• driven low
• toggled (high-to-low or low-to-high)
• remain unchanged (that is, reflects the state of the
The action on the pin is based on the value of the mode
select bits (CCPxM<3:0>). At the same time, the inter-
rupt flag bit, CCPxIF, is set.
11.3.1
The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.
FIGURE 11-2:
 2010 Microchip Technology Inc.
I/O latch)
Note:
Compare Mode
CCP PIN CONFIGURATION
Clearing the CCPxCON register will force
the CCPx compare output latch (depend-
ing on device configuration) to the default
low level. This is not the PORTB or
PORTC I/O data latch.
0
1
COMPARE MODE OPERATION BLOCK DIAGRAM
CCPR2H
CCPR1H
TMR1H
TMR3H
T3CCP1
Comparator
Comparator
CCPR2L
CCPR1L
TMR1L
TMR3L
Compare
Compare
Match
Match
0
1
Set CCP1IF
T3CCP2
Set CCP2IF
(Timer1/Timer3 Reset, A/D Trigger)
11.3.2
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation will not work reliably.
11.3.3
When the Generate Software Interrupt mode is chosen
(CCPxM<3:0> = 1010), the corresponding CCPx pin is
not affected. Only the CCPxIF interrupt flag is affected.
11.3.4
Both CCP modules are equipped with a Special Event
Trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the
(CCPxM<3:0> = 1011).
For either CCP module, the Special Event Trigger resets
the timer register pair for whichever timer resource is
currently assigned as the module’s time base. This
allows the CCPRx registers to serve as a programmable
period register for either timer.
The Special Event Trigger for CCP2 can also start an
A/D conversion. In order to do this, the A/D converter
must already be enabled.
PIC18F2XK20/4XK20
(Timer1/Timer3 Reset)
Special Event Trigger
Special Event Trigger
CCP1CON<3:0>
CCP2CON<3:0>
Compare
Output
Output
Logic
4
Logic
4
TIMER1/TIMER3 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
Special
S
R
S
R
Q
Q
Output Enable
Output Enable
Event
TRIS
TRIS
DS41303G-page 147
Trigger
CCP1 pin
CCP2 pin
mode