PIC18F46K20-E/MV Microchip Technology, PIC18F46K20-E/MV Datasheet - Page 446

• Manufacturer Part Number: PIC18F46K20-E/MV
• Description: 64KB, Flash, 3968bytes-RAM, 36I/O, 8-bit Family,nanowatt XLP 40 UQFN 5x5x0.5mm T
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F46K20-E/MV

• Processor Series: PIC18
• Core: PIC18F
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Data Ram Size: 512 B
• Interface Type: I2C, SPI, SCI, USB, MSSP, RJ11
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: UQFN-40
• Development Tools By Supplier: MPLAB Integrated Development Environment
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 125 C
• Supply Current (max): 30 uA
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / Rohs Status: Details

PIC18F2XK20/4XK20
Extended Instruction Set
F
Fail-Safe Clock Monitor .............................................. 40, 299
Fast Register Stack ............................................................ 68
Firmware Instructions ....................................................... 315
Flash Program Memory ...................................................... 89
G
General Call Address Support ......................................... 218
GOTO ............................................................................... 336
H
Hardware Multiplier .......................................................... 105
High/Low-Voltage Detect ................................................. 293
DS41303G-page 446
Interrupts
Synchronous Master Mode .............................. 257, 262
Synchronous Slave Mode
ADDFSR .................................................................. 358
ADDULNK ................................................................ 358
and Using MPLAB Tools .......................................... 364
CALLW ..................................................................... 359
Considerations for Use ............................................ 362
MOVSF .................................................................... 359
MOVSS .................................................................... 360
PUSHL ..................................................................... 360
SUBFSR .................................................................. 361
SUBULNK ................................................................ 361
Syntax ...................................................................... 357
Fail-Safe Condition Clearing ...................................... 40
Fail-Safe Detection .................................................... 40
Fail-Safe Operation .................................................... 40
Reset or Wake-up from Sleep .................................... 40
Associated Registers ................................................. 97
Control Registers ....................................................... 90
Erase Sequence ........................................................ 94
Erasing ....................................................................... 94
Operation During Code-Protect ................................. 97
Reading ...................................................................... 93
Table Pointer
Table Pointer Boundaries .......................................... 92
Table Reads and Table Writes .................................. 89
Write Sequence ......................................................... 95
Writing To ................................................................... 95
Introduction .............................................................. 105
Operation ................................................................. 105
Performance Comparison ........................................ 105
Applications .............................................................. 297
Associated Registers ............................................... 297
Synchronous Mode .......................................... 257
Asychronous Receive ...................................... 243
Asychronous Transmit ..................................... 239
Associated Registers, Receive ........................ 261
Associated Registers, Transmit ............... 259, 262
Reception ......................................................... 260
Transmission .................................................... 257
Associated Registers, Receive ........................ 263
Reception ......................................................... 263
Transmission .................................................... 262
EECON1 and EECON2 ..................................... 90
TABLAT (Table Latch) Register ......................... 92
TBLPTR (Table Pointer) Register ...................... 92
Boundaries Based on Operation ........................ 92
Protection Against Spurious Writes ................... 97
Unexpected Termination .................................... 97
Write Verify ........................................................ 97
HLVD. See High/Low-Voltage Detect. ............................. 293
HLVDCON Register ......................................................... 293
I
I/O Ports ........................................................................... 121
I
I
ID Locations ............................................................. 299, 313
INCF ................................................................................ 336
INCFSZ ............................................................................ 337
In-Circuit Debugger .......................................................... 313
In-Circuit Serial Programming (ICSP) ...................... 299, 313
Indexed Literal Offset Addressing
Indexed Literal Offset Mode ............................................. 362
Indirect Addressing ............................................................ 84
INFSNZ ............................................................................ 337
Initialization Conditions for all Registers ...................... 59–62
Instruction Cycle ................................................................ 69
Instruction Flow/Pipelining ................................................. 69
Instruction Set .................................................................. 315
2
2
C
C Mode (MSSP)
Characteristics ......................................................... 382
Current Consumption ............................................... 295
Effects of a Reset .................................................... 297
Operation ................................................................. 294
Setup ....................................................................... 295
Start-up Time ........................................................... 295
Typical Application ................................................... 297
Associated Registers ............................................... 235
Acknowledge Sequence Timing .............................. 228
Baud Rate Generator .............................................. 221
Bus Collision
Clock Arbitration ...................................................... 222
Clock Stretching ....................................................... 214
Clock Synchronization and the CKP bit (SEN = 1) .. 215
Effects of a Reset .................................................... 229
General Call Address Support ................................. 218
I
Master Mode ............................................................ 219
Multi-Master Communication, Bus Collision
Multi-Master Mode ................................................... 229
Operation ................................................................. 207
Read/Write Bit Information (R/W Bit) ............... 207, 208
Registers ................................................................. 202
Serial Clock (RC3/SCK/SCL) ................................... 208
Slave Mode .............................................................. 207
Sleep Operation ....................................................... 229
Stop Condition Timing ............................................. 228
and Standard PIC18 Instructions ............................. 362
Clocking Scheme ....................................................... 69
ADDLW .................................................................... 321
2
C Clock Rate w/BRG ............................................. 221
During Sleep .................................................... 297
During a Repeated Start Condition .................. 232
During a Stop Condition .................................. 234
10-Bit Slave Receive Mode (SEN = 1) ............ 214
10-Bit Slave Transmit Mode ............................ 214
7-Bit Slave Receive Mode (SEN = 1) .............. 214
7-Bit Slave Transmit Mode .............................. 214
Operation ......................................................... 220
Reception ........................................................ 225
Repeated Start Condition Timing .................... 224
Start Condition Timing ..................................... 223
Transmission ................................................... 225
and Arbitration ................................................. 229
Addressing ....................................................... 207
Reception ........................................................ 208
Transmission ................................................... 208
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