PIC24F16KA301-E/P Microchip Technology, PIC24F16KA301-E/P Datasheet
PIC24F16KA301-E/P
Specifications of PIC24F16KA301-E/P
Related parts for PIC24F16KA301-E/P
PIC24F16KA301-E/P Summary of contents
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... General Purpose, 2011 Microchip Technology Inc. PIC24FV32KA304 Data Sheet 16-Bit Flash Microcontrollers with XLP Technology DS39995B ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Three 16-Bit Capture Inputs with Dedicated Timers • Three 16-Bit Compare/PWM Output with Dedicated Timers • Configurable Open-Drain Outputs on Digital I/O Pins • Three External Interrupt Sources 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY Analog Features: • 12-Bit 16-Channel Analog-to-Digital Converter: - 100 ksps conversion rate ...
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... PIC24FV32KA304 FAMILY Memory PIC24F Device PIC24FV16KA301 20 16K 2K /PIC24F16KA301 PIC24FV32KA301 20 32K 2K /PIC24F32KA301 PIC24FV16KA302 28 16K 2K /PIC24F16KA302 PIC24FV32KA302 28 32K 2K /PIC24F32KA302 PIC24FV16KA304 44 16K 2K /PIC24F16KA304 PIC24FV32KA304 44 32K 2K /PIC24F32KA304 DS39995B-page 4 512 512 512 512 512 512 2011 Microchip Technology Inc. ...
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... CN12/RB14 18 AN9/C3INA/SCL2/T3CK/T2CK/REFO/SS1/CTED6/CN11/RB15 Pin numbers in bold indicate pin function differences between PIC24FV and PIC24F devices. Legend: PIC24F32KA304 device pins have a maximum voltage of 3.6V and are not 5V tolerant. Note 1: 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY MCLR/RA5 RA0 SS RA1 3 18 RB15 RB0 ...
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... REF REF CV -/V -/AN1/CN3/RA1 REF REF PGED1/AN2/ULPWU/CTCMP/C1IND/C2INB/C3IND/U2TX/CN4/RB0 PGEC1/AN3/C1INC/C2INA/U2RX/CTED12/CN5/RB1 AN4/C1INB/C2IND/SDA2/T5CK/T4CK/U1RX/CTED13/CN6/RB2 AN5/C1INA/C2INC/SCL2/CN7/RB3 V SS OSCI/AN13/CLKI/CN30/RA2 OSCO/AN14/CLKO/CN29/RA3 SOSCI/AN15/U2RTS/CN1/RB4 SOSCO/SCLKI/U2CTS/CN0/RA4 V DD PGED3/ASDA (1) /SCK2/CN27/RB5 (1) PGEC3/ASCL /SDO2/CN24/RB6 U1TX/INT0/CN23/RB7 SCL1/U1CTS/C3OUT/CTED10/CN22/RB8 SDA1/T1CK/U1RTS/IC2/CTED4/CN21/RB9 SDI2/IC1/CTED3/CN9/RA7 C2OUT/OC1/CTED1/INT2/CN8/RA6 PGED2/SDI1/OC3/CTED11/CN16/RB10 PGEC2/SCK1/OC2/CTED9/CN15/RB11 AN12/LVDIN/SS2/IC3/CTED2/CN14/RB12 AN11/SDO1/OCFB/CTPLS/CN13/RB13 /AN10/C3INB/RTCC/C1OUT/OCFA/CTED5/INT1/CN12/ REF RB14 AN9/C3INA/T3CK/T2CK/REFO/SS1/CTED6/CN11/RB15 PIC24FXXKA302 2011 Microchip Technology Inc. ...
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... Exposed pad on underside of device is connected to V Note 1: Alternative multiplexing for SDA1 (ASDA1) and SCL1 (ASCL1) when the I2CSEL Configuration bit is set. 2: PIC24F32KA304 device pins have a maximum voltage of 3.6V and are not 5V tolerant. 3: 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY (1,2,3) 28-Pin QFN 28 27 ...
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... PP V +/CV +/AN0/C3INC/CN2/ REF REF RA0 CV -/V -/AN1/CN3/RA1 REF REF PGED1/AN2/ULPWU/CTCMP/C1IND/ C2INB/C3IND/U2TX/CN4/RB0 PGEC1/AN3/C1INC/C2INA/U2RX/ CTED12/CN5/RB1 AN4/C1INB/C2IND/SDA2/T5CK/ T4CK/CTED13/CN6/RB2 AN5/C1INA/C2INC/SCL2/CN7/RB3 AN6/CN32/RC0 AN7/CN31/RC1 AN8/CN10/RC2 OSCI/AN13/CLKI/CN30/RA2 OSCO/AN14/CLKO/CN29/RA3 OCFB/CN33/RA8 SOSCI/AN15/U2RTS/CN1/RB4 SOSCO/SCLKI/U2CTS/CN0/RA4 SS2/CN34/RA9 SDI2/CN28/RC3 SDO2/CN25/RC4 SCK2/CN26/RC5 (2) PGED3/ASDA1 /CN27/RB5 (2) PGEC3/ASCL1 /CN24/RB6 INT0/CN23/RB7 SCL1/U1CTS/C3OUT/CTED10/ CN22/RB8 2011 Microchip Technology Inc. ...
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... Note 1: connected Alternative multiplexing for SDA1 2: (ASDA1) and SCL1 (ASCL1) when the I2CSEL Configuration bit is set. PIC24F32KA3XX device pins have a 3: maximum voltage of 3.6V and are not 5V tolerant. 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY Pin PIC24FVXXKA304 1 SDA1/T1CK/U1RTS/CTED4/CN21/RB9 2 U1RX/CN18/RC6 3 U1TX/CN17/RC7 4 OC2/CN20/RC8 ...
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... Instruction Set Summary .......................................................................................................................................................... 255 29.0 Electrical Characteristics .......................................................................................................................................................... 263 30.0 Packaging Information.............................................................................................................................................................. 289 Appendix A: Revision History............................................................................................................................................................. 311 Index .................................................................................................................................................................................................. 313 The Microchip Web Site ..................................................................................................................................................................... 317 Customer Change Notification Service .............................................................................................................................................. 317 Customer Support .............................................................................................................................................................................. 317 Reader Response .............................................................................................................................................................................. 318 Product Identification System............................................................................................................................................................. 319 DS39995B-page 10 2011 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY to receive the most current information on all of our products. DS39995B-page 11 ...
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... PIC24FV32KA304 FAMILY NOTES: DS39995B-page 12 2011 Microchip Technology Inc. ...
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... DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC24FV16KA301, PIC24F16KA301 • PIC24FV16KA302, PIC24F16KA302 • PIC24FV16KA304, PIC24F16KA304 • PIC24FV32KA301, PIC24F32KA301 • PIC24FV32KA302, PIC24F32KA302 • PIC24FV32KA304, PIC24F32KA304 The PIC24FV32KA304 family introduces a new line of extreme low-power Microchip devices. This is a 16-bit microcontroller family with a broad peripheral feature set and enhanced computational performance ...
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... This information is provided in the pinout diagrams on pages the data sheet. Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first. 2011 Microchip Technology Inc. Kbytes for Kbytes for on the ...
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... Input Change Notification Interrupt Serial Communications: UART SPI (3-wire/4-wire C™ 12-Bit Analog-to-Digital Module (input channels) Analog Comparators Resets (and delays) Instruction Set Packages 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY DC – 32 MHz 16K 32K 16K 5632 11264 5632 2048 512 30 (26/4) PORTA< ...
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... POR, BOR, RESET Instruction, MCLR, WDT, Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations 20-Pin PDIP/SSOP/SOIC SPDIP/SSOP/SOIC/QFN 32K 16K 32K 11264 5632 11264 PORTA<11:0>, PORTB<15:0>, PORTC<9:0> 28-Pin 44-Pin QFN/TQFP 48-Pin UQFN 2011 Microchip Technology Inc. ...
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... Regulator V CAP HLVD RTCC Timer1 IC1-3 REFO Note 1: All pins or features are not implemented on all device pinout configurations. See descriptions. 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY Data Bus Data Latch Data RAM PCH PCL Program Counter Address Stack Repeat Latch ...
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TABLE 1-3: PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS F Pin Number Function 20-Pin 28-Pin 20-Pin 28-Pin PDIP/SSOP/ SPDIP/SSOP/ QFN QFN SOIC SOIC AN0 AN1 AN2 AN3 ...
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TABLE 1-3: PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED) F Pin Number Function 20-Pin 28-Pin 20-Pin 28-Pin PDIP/SSOP/ SPDIP/SSOP/ QFN QFN SOIC SOIC C3INA C3INB C3INC C3IND ...
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TABLE 1-3: PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED) F Pin Number Function 20-Pin 28-Pin 20-Pin 28-Pin PDIP/SSOP/ SPDIP/SSOP/ QFN QFN SOIC SOIC CN18 — — — — CN19 –- –- — — CN20 –- –- — — CN21 ...
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TABLE 1-3: PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED) F Pin Number Function 20-Pin 28-Pin 20-Pin 28-Pin PDIP/SSOP/ SPDIP/SSOP/ QFN QFN SOIC SOIC CTED2 CTED3 — — CTED4 CTED5 ...
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TABLE 1-3: PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED) F Pin Number Function 20-Pin 28-Pin 20-Pin 28-Pin PDIP/SSOP/ SPDIP/SSOP/ QFN QFN SOIC SOIC PGED2 3 20 21,3 18,28 PGEC3 10 7 12,15 9,12 PGED3 9 6 11,14 8,11 RA0 ...
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TABLE 1-3: PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED) F Pin Number Function 20-Pin 28-Pin 20-Pin 28-Pin PDIP/SSOP/ SPDIP/SSOP/ QFN QFN SOIC SOIC RC0 — — — — RC1 — — — — RC2 — — — — RC3 — — — ...
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TABLE 1-3: PIC24FV32KA304 FAMILY PINOUT DESCRIPTIONS (CONTINUED) F Pin Number Function 20-Pin 28-Pin 20-Pin 28-Pin PDIP/SSOP/ SPDIP/SSOP/ QFN QFN SOIC SOIC T5CK U1CTS U1RTS U1RX ...
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... REF REF reference for analog modules is implemented The AV and AV pins must always be Note connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure 2-1. 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY FIGURE 2- MCLR ( Pin” ...
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... The DD may be beneficial. A typical Figure 2-1. Other circuit ) and fast signal transitions must IL (Figure 2-2). is replaced for normal run-time EXAMPLE OF MCLR PIN CONNECTIONS R1 R2 MCLR PIC24FXXKXX JP C1 and V specifications are met and V specifications are met. IL 2011 Microchip Technology Inc. ...
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... TABLE 2-1: SUITABLE CAPACITOR EQUIVALENTS Make Part # TDK C3216X7R1C106K TDK C3216X5R1C106K Panasonic ECJ-3YX1C106K Panasonic ECJ-4YB1C106K Murata GRM32DR71C106KA01L Murata GRM31CR61C106KC31L 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY Refer to ) Section 29.0 “Electrical Characteristics” CAP information on V FIGURE 2- 0.1 Table 2-1. 0.01 0.001 . ...
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... ICSP to the Microchip debugger/emulator tool. For more information development tools connection requirements, refer to Section 27.0 “Development Support”. DC BIAS VOLTAGE vs. CAPACITANCE CHARACTERISTICS 16V Capacitor 10V Capacitor Bias Voltage (VDC) Table 2-1. ) requirements available Microchip 2011 Microchip Technology Inc. ...
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... Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1 kΩ kΩ resistor unused pins and drive the SS output to logic low. 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY FIGURE 2-5: for Single-Sided and In-Line Layouts: Copper Pour ...
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... PIC24FV32KA304 FAMILY NOTES: DS39995B-page 30 2011 Microchip Technology Inc. ...
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... Register Indirect modes. Each group offers up to seven addressing modes. Instructions are associated with predefined addressing modes depending upon their functional requirements. 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY For most instructions, the core is capable of executing a data (or program data) memory read, a working ...
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... ALU Description Working Register Array 23-Bit Program Counter ALU STATUS Register Stack Pointer Limit Value Register Table Memory Page Address Register Program Space Visibility Page Address Register Repeat Loop Counter Register CPU Control Register Peripheral Modules 2011 Microchip Technology Inc. ...
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... PROGRAMMER’S MODEL W0 (WREG) Divider Working Registers W1 W2 Multiplier Registers W10 W11 W12 W13 W14 W15 22 Registers or bits are shadowed for PUSH.S and POP.S instructions. 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY 15 0 Frame Pointer 0 Stack Pointer 0 SPLIM TBLPAG 7 0 PSVPAG 15 0 RCOUNT ...
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... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared th low-order bit (for byte-sized data low-order bit of the result has occurred (1,2) U-0 U-0 R/W-0, HSC — — DC bit bit Bit is unknown th low-order bit (for word-sized data) 2011 Microchip Technology Inc. ...
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... Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY U-0 U-0 U-0 — ...
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... All multi-bit shift instructions only support Register Direct Addressing for both the operand source and result destination. A full summary of instructions that use the shift operation is provided in Table 3-2. Description 2011 Microchip Technology Inc. ...
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... Unimplemented Read ‘0’ Data EEPROM Reserved Device Config Registers Reserved DEVID (2) Figure 4-1. 000000h 000002h 000004h 0000FEh 000100h 000104h 0001FEh 000200h 002BFEh 0057FEh 7FFE00h 7FFFFFh 800000h F7FFFEh F80000h F80010h F80012h FEFFFEh FF0000h FFFFFFh 2011 Microchip Technology Inc. ...
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... Program Memory ‘Phantom’ Byte (read as ‘0’) 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY 4.1.3 DATA EEPROM In the PIC24FV32KA304 family, the data EEPROM is mapped to the top of the user program memory space, organized in starting at address, 7FFE00, and expanding up to address, 7FFFFF ...
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... Most Significant Bytes (MSBs) have odd addresses. LSB MSB LSB Address 0000h SFR SFR Space Space 07FEh 0800h Data RAM 0FFEh 1FFEh Unimplemented Read as ‘0’ 7FFFh 8000h Program Space Visibility Area FFFEh space is organized in Near Data Space 2011 Microchip Technology Inc. ...
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... RTC/Comp 600h — — 700h Legend: — implemented SFRs in this block. 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY Although most instructions are capable of operating on word or byte data sizes, it should be noted that some instructions operate only on words. ® devices 4.2.3 ...
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TABLE 4-3: CPU CORE REGISTERS MAP Start File Name Bit 15 Bit 14 Bit 13 Bit 12 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 ...
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TABLE 4-4: ICN REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name (1) CNPD1 0056 CN15PDE CN14PDE CN13PDE CN12PDE CNPD2 0058 CN31PDE (1,2) CN30PDE CN29PDE CN28PDE (1,2) CNPD3 005A — — — — (1) CNEN1 0062 ...
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TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name INTCON1 0080 NSTDIS — — — INTCON2 0082 ALTIVT DISI — — IFS0 0084 NVMIF — AD1IF U1TXIF U1RXIF IFS1 0086 U2TXIF U2RXIF ...
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TABLE 4-6: TIMER REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON — ...
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TABLE 4-8: OUTPUT COMPARE REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 OC1CON1 0190 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 ENFLT0 OC1CON2 0192 FLTMD FLTOUT FLTTRIEN OCINV OC1RS 0194 OC1R 0196 OC1TMR 0198 ...
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TABLE 4-9: I C™ REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 I2C1RCV 0200 — — — — I2C1TRN 0202 — — — — I2C1BRG 0204 — — — — I2C1CON 0206 I2CEN — ...
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TABLE 4-11: SPI REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name SPI1STAT 0240 SPIEN — SPISIDL — SPI1CON1 0242 — — — DISSCK SPI1CON2 0244 FRMEN SPIFSD SPIFPOL — SPI1BUF 0248 SPI2STAT 0260 SPIEN — ...
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TABLE 4-14: PORTC REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name TRISC 02D0 — — — — PORTC 02D2 — — — — LATC 02D4 — — — — ODCC 02D6 — — — ...
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TABLE 4-16: ADC REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUF10 0314 ADC1BUF11 0316 ...
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TABLE 4-17: CTMU REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 CTMUCON1 035A CTMUEN — CTMUSIDL TGEN CTMUCON2 035C EDG1EDGE EDG1POL EDG1SEL3 EDG1SEL2 EDG1SEL1 EDG1SEL0 CTMUICON 035E ITRIM5 ITRIM4 ITRIM3 ITRIM2 AD1CTMUENH 0360 — — ...
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TABLE 4-21: CRC REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name CRCCON1 0640 CRCEN — CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT CRCISEL CRCGO LENDIAN CRCCON2 0642 — — — DWIDTH4 DWIDTH3 DWIDTH2 DWIDTH1 ...
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TABLE 4-24: NVM REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 NVMCON 0760 WR WREN WRERR PGMONLY NVMKEY 0766 — — — — — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. ...
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... Table 4-27 and Figure 4-5 show how the program EA is created for table operations and remapping accesses from the data EA. Here, P<23:0> bits refer to a program space word, whereas the D<15:0> bits refer to a data space word. 2011 Microchip Technology Inc. ...
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... Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY Program Space Address <23> ...
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... D<15:8>, the ‘phantom’ byte, will always be ‘0’. In Byte mode, it maps the upper or lower byte of the program word to D<7:0> of the data address, as above. Note that the data will always be ‘0’ when the upper ‘phantom’ byte is selected (byte select = 1). 2011 Microchip Technology Inc. ...
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... When FIGURE 4-6: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY TBLPAG<7> the table page is located in the user memory space. When TBLPAG<7> the page is located in configuration space. Only table read operations will execute in Note: ...
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... PSVPAG is mapped into the upper half of the data memory space.... 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY Although each data space address, 8000h and higher, maps directly into a corresponding program memory address (see Figure 4-7), only the lower 16 bits of the 24-bit program word are used to contain the data ...
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... PIC24FV32KA304 FAMILY NOTES: DS39995B-page 58 2011 Microchip Technology Inc. ...
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... Using Table Instruction User/Configuration Space Select 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY Run Time Self Programming (RTSP) is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may write program memory data in blocks of 32 instructions (96 bytes time, and erase program memory in blocks of 32, 64 and 128 instructions (96,192 and 384 bytes time ...
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... During a programming or erase operation, the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON<15>) starts the operation and the WR bit is automatically cleared when the operation is finished. required for (Register 5-1) controls the blocks Operations”. 2011 Microchip Technology Inc. ...
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... All other combinations of NVMOP<5:0> are no operation. Note 1: Available in ICSP™ mode only. Refer to device programming specification. 2: The address in the Table Pointer decides which rows will be erased. 3: This bit is used only while accessing data EEPROM. 4: 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY R/W-0 U-0 U-0 (4) PGMONLY — ...
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... Initialize PM Page Boundary SFR ; Initialize in-page EA[15:0] pointer ; Set base address of erase block ; Block all interrupts for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted Example 5-1). 2011 Microchip Technology Inc. ...
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... MOV #LOW_WORD_31, W2 MOV #HIGH_BYTE_31, W3 TBLWTL W2, [W0] TBLWTH W3, [W0] 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY // Initialize PM Page Boundary SFR // Initialize lower word of address // Set base address of erase block // with dummy latch write // Initialize NVMCON // Block all interrupts for next 5 ...
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... Initialize lower word of address // Write to address low word // Write to upper byte // Increment address ; Block all interrupts for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; 2 NOPs required after setting Wait for the sequence to be completed ; 2011 Microchip Technology Inc. ...
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... MOV #0x55, W0 MOV W0, NVMKEY MOV #0xAA, W0 MOV W0, NVMKEY BSET NVMCON, #WR 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY ; ;Initialize PM Page Boundary SFR ;Initialize a register with program memory address ; ; ; Write PM low word into program latch ; Write PM high byte into program latch ; ; Set NVMOP bits to 0011 ...
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... PIC24FV32KA304 FAMILY NOTES: DS39995B-page 66 2011 Microchip Technology Inc. ...
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... W0, NVMKEY "mov #0xAA, W1 "mov W1, NVMKEY // Perform Write/Erase operations asm volatile ("bset NVMCON, #WR "nop "nop 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY 6.1 NVMCON Register The NVMCON register control register for data EEPROM program/erase operations. The upper byte contains the control bits ...
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... DS39995B-page 68 R/W-0 U-0 U-0 PGMONLY — — R/W-0 R/W-0 R/W-0 NVMOP4 NVMOP3 NVMOP2 U = Unimplemented bit, read as ‘0’ Settable bit ‘0’ = Bit is cleared 2011 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 R/W-0 NVMOP1 NVMOP0 bit Bit is unknown ...
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... Erase one, four or eight words • Bulk erase the entire data EEPROM • Write one word • Read one word 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY Like program memory operations, the Least Significant bit (LSb) of NVMADR is restricted to even addresses. ...
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... Initialize EE Data page pointer // Initizlize lower word of address // Write EEPROM data to write latch // Disable Interrupts For 5 Instructions // Issue Unlock Sequence & Start Write Cycle // Optional: Poll WR bit to wait for // write sequence to complete 2011 Microchip Technology Inc. Example 6-2. ...
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... Set up a pointer to the EEPROM location to be erased TBLPAG = __builtin_tblpage(&eeData); offset = __builtin_tbloffset(&eeData); __builtin_tblwtl(offset, newData); asm volatile ("disi #5"); __builtin_write_NVM(); while(NVMCONbits.WR=1); 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY 6.4.2 SINGLE-WORD WRITE To write a single word in the data EEPROM, the following sequence must be followed: 1. ...
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... Example Program Space Visibility (PSV) can also be used to read locations in the data EEPROM. // Global variable located in EEPROM // Initialize EE Data page pointer // Initizlize lower word of address // Write EEPROM data to write latch 2011 Microchip Technology Inc. and table read 6-5. ...
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... Configuration Mismatch Uninitialized W Register 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. Most registers are unaffected by a Reset; their status is ...
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... R/C-0, HS (3) LVREN — DPSLP R/W-0, HS R/W-0, HS R/W-0, HS (2) WDTO SLEEP IDLE HS = Hardware Settable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (3) (2) R/W-0 R/W-0 CM PMSLP bit 8 R/W-1, HS R/W-1, HS BOR POR bit Bit is unknown (3) 2011 Microchip Technology Inc. ...
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... Reset is chosen, as shown in Table switching is disabled, the system clock source is always selected according to the oscillator Configuration bits. For more information, see Section 9.0 “Oscillator Configuration”. 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY (1) (CONTINUED) Setting Event TABLE 7-2: 7-2. If clock ...
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... POR PWRT OST POR PWRT OST LOCK T — PWRT T T PWRT FRC T T PWRT LPRC T T PWRT LOCK PWRT FRC LOCK T T PWRT OST PWRT FRC LOCK — — Section 29.0 “Electrical 2011 Microchip Technology Inc. Notes None Characteristics”. ...
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... DSLPBOR (FDS<6> DSLPBOR will re-arm the POR to ensure the device will reset if V drops below the POR threshold. DD 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY 7.5 Brown-out Reset (BOR) The PIC24FV32KA304 family devices implement a BOR circuit, which provides the user several configuration and power-saving options. The BOR is controlled by the BORV< ...
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... Sleep mode by eliminating the small incremental BOR current. BOR levels differ depending on device type; Note: PIC24FV32KA3XX devices are at different levels than those of PIC24F32KA3XX devices. See Section 29.0 “Electrical for BOR voltage levels. Characteristics” 2011 Microchip Technology Inc. as previously ...
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... Table 8-1 and Table 8-2. 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY 8.1.1 ALTERNATE INTERRUPT VECTOR TABLE (AIVT) The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in comprehensive AIVT ...
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... Note 1: See Table 8-2 for the interrupt vector list. DS39995B-page 80 000000h 000002h 000004h 000014h 00007Ch Interrupt Vector Table (IVT) 00007Eh 000080h 0000FCh 0000FEh 000100h 000102h 000114h Alternate Interrupt Vector Table (AIVT) 00017Ch 00017Eh 000180h 0001FEh 000200h 2011 Microchip Technology Inc. (1) (1) ...
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... Timer1 Timer2 Timer3 Timer4 Timer5 UART1 Error UART1 Receiver UART1 Transmitter UART2 Error UART2 Receiver UART2 Transmitter Ultra Low-Power Wake-up 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY AIVT Address 000104h Reserved 000106h Oscillator Failure 000108h Address Error 00010Ah Stack Error 00010Ch ...
Page 82
... IPL<2:0>, also indicates the current CPU priority level. IPL3 is a read-only bit so that the trap events cannot be masked by the user’s software. All interrupt registers are described in through Register 8-33, in the following sections. 2011 Microchip Technology Inc. Register 8-1 ...
Page 83
... The IPL bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU interrupt priority level. 2: The value in parentheses indicates the interrupt priority level if IPL3 = 1. The IPL Status bits are read-only when NSTDIS (INTCON1<15> Bit 8 and bits 4 through 0 are described in Note: 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY U-0 U-0 U-0 — — ...
Page 84
... U-0 R/C-0, HSC R/W-0 (2) (1) — IPL3 PSV HSC = Hardware Settable/Clearable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) “CPU”. U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown 2011 Microchip Technology Inc. ...
Page 85
... Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY U-0 U-0 U-0 — — ...
Page 86
... Interrupt on positive edge DS39995B-page 86 U-0 U-0 U-0 — — — U-0 U-0 R/W-0 — — INT2EP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 R/W-0 INT1EP INT0EP bit Bit is unknown ...
Page 87
... T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY R/W-0, HS R/W-0, HS R/W-0, HS U1TXIF U1RXIF ...
Page 88
... Interrupt request has not occurred DS39995B-page 88 R/W-0, HS R/W-0, HS U-0 T5IF T4IF — R/W-0, HS R/W-0, HS R/W-0, HS INT1IF CNIF CMIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0, HS U-0 OC3IF — bit 8 R/W-0 R/W-0 MI2C1IF SI2C1IF bit Bit is unknown 2011 Microchip Technology Inc. ...
Page 89
... SPI2IF: SPI2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SPF2IF: SPI2 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY U-0 U-0 U-0 — — ...
Page 90
... Unimplemented: Read as ‘0’ DS39995B-page 90 U-0 U-0 U-0 — — — U-0 U-0 R/W-0, HS — — MI2C2IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0, HS U-0 SI2C2IF — bit Bit is unknown ...
Page 91
... Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 U1ERIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY U-0 U-0 U-0 — — — ...
Page 92
... Interrupt request has not occurred DS39995B-page 92 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011 Microchip Technology Inc. U-0 U-0 — — bit 8 U-0 R/W-0, HS — ULPWUIF bit Bit is unknown ...
Page 93
... T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE ...
Page 94
... Interrupt request is not enabled DS39995B-page 94 R/W-0 R/W-0 U-0 T5IE T4IE — R/W-0 R/W-0 R/W-0 INT1IE CNIE CMIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 U-0 OC3IE — bit 8 R/W-0 R/W-0 MI2C1IE SI2C1IE bit Bit is unknown 2011 Microchip Technology Inc. ...
Page 95
... SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 SPF2IE: SPI2 Fault Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY U-0 U-0 U-0 — — — ...
Page 96
... Unimplemented: Read as ‘0’ DS39995B-page 96 U-0 U-0 U-0 — — — U-0 U-0 R/W-0 — — MI2C2IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 U-0 SI2C2IE — bit Bit is unknown ...
Page 97
... U2ERIE: UART2 Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 U1ERIE: UART1 Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 Unimplemented: Read as ‘0’ 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY U-0 U-0 U-0 — — — U-0 ...
Page 98
... Interrupt request is not enabled DS39995B-page 98 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011 Microchip Technology Inc. U-0 U-0 — — bit 8 U-0 R/W-0 — ULPWUIE bit Bit is unknown ...
Page 99
... Unimplemented: Read as ‘0’ bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY R/W-0 U-0 R/W-1 T1IP0 — OC1IP2 R/W-0 ...
Page 100
... Unimplemented: Read as ‘0’ DS39995B-page 100 R/W-0 U-0 R/W-1 T2IP0 — OC2IP2 R/W-0 U-0 U-0 IC2IP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC2IP1 OC2IP0 bit 8 U-0 U-0 — — bit Bit is unknown 2011 Microchip Technology Inc. ...
Page 101
... Unimplemented: Read as ‘0’ bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY R/W-0 U-0 R/W-1 U1RXIP0 — SPI1IP2 R/W-0 ...
Page 102
... Interrupt source is disabled DS39995B-page 102 R/W-0 U-0 U-0 NVMIP0 — — R/W-0 U-0 R/W-1 AD1IP0 — U1TXIP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 R/W-0 U1TXIP1 U1TXIP0 bit Bit is unknown 2011 Microchip Technology Inc. ...
Page 103
... Unimplemented: Read as ‘0’ bit 2-0 SI2C1P<2:0>: Slave I2C1 Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY R/W-0 U-0 R/W-1 CNIP0 — CMIP2 R/W-0 ...
Page 104
... Interrupt source is disabled DS39995B-page 104 U-0 U-0 U-0 — — — U-0 U-0 R/W-1 — — INT1IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 R/W-0 INT1IP1 INT1IP0 bit Bit is unknown ...
Page 105
... OC3IP: Output Compare Channel 3 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY R/W-0 U-0 U-0 T4IP0 — — R/W-0 ...
Page 106
... Interrupt source is disabled DS39995B-page 106 R/W-0 U-0 R/W-1 U2TXIP0 — U2RXIP2 R/W-0 U-0 R/W-1 INT2IP0 — T5IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 U2RXIP1 U2RXIP0 bit 8 R/W-0 R/W-0 T5IP1 T5IP0 bit Bit is unknown 2011 Microchip Technology Inc. ...
Page 107
... Unimplemented: Read as ‘0’ bit 2-0 SPF2IP<2:0>: SPI2 Fault Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY U-0 U-0 U-0 — — — R/W-0 ...
Page 108
... Unimplemented: Read as ‘0’ DS39995B-page 108 U-0 U-0 U-0 — — — R/W-0 U-0 U-0 IC3IP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown 2011 Microchip Technology Inc. ...
Page 109
... SI2C2IP<2:0>: Slave I2C2 Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY U-0 U-0 R/W-1 — — MI2C2IP2 R/W-0 ...
Page 110
... Unimplemented: Read as ‘0’ DS39995B-page 110 U-0 U-0 R/W-1 — — RTCIP2 U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011 Microchip Technology Inc. R/W-0 R/W-0 RTCIP1 RTCIP0 bit 8 U-0 U-0 — — bit Bit is unknown ...
Page 111
... U1ERIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY R/W-0 U-0 R/W-1 CRCIP0 — U2ERIP2 R/W-0 ...
Page 112
... CTMUIP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 R/W-0 HLVDIP1 HLVDIP0 bit Bit is unknown U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown 2011 Microchip Technology Inc. ...
Page 113
... Unimplemented: Read as ‘0’ bit 6-4 ULPWUIP<2:0>: Ultra Low-Power Wake-up Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY U-0 U-0 U-0 — — — U-0 ...
Page 114
... Interrupt vector pending is number 8 DS39995B-page 114 U-0 R-0 R-0 — ILR3 ILR2 R-0 R-0 R-0 VECNUM4 VECNUM3 VECNUM2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R-0 R-0 ILR1 ILR0 bit 8 R-0 R-0 VECNUM1 VECNUM0 bit Bit is unknown 2011 Microchip Technology Inc. ...
Page 115
... If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY 8.4.3 TRAP SERVICE ROUTINE (TSR) A Trap Service Routine (TSR) is coded like an ISR, ...
Page 116
... PIC24FV32KA304 FAMILY NOTES: DS39995B-page 116 2011 Microchip Technology Inc. ...
Page 117
... Secondary Oscillator SOSCO SOSCEN Enable SOSCI Oscillator 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY • Software-controllable switching between various clock sources. • Software-controllable postscaler for selective clocking of CPU for system power savings. • System frequency range declaration bits for EC comprehensive mode ...
Page 118
... Primary 00 Internal 11 Internal 11 bit settings. The oscillator Bits”). The Primary bits, POSCMD<1:0> the Initial Oscillator Select range Configuration bits, Table 9-1. FNOSC<2:0> Notes 1, 2 111 1 110 1 101 1 100 011 011 010 010 010 1 001 1 000 2011 Microchip Technology Inc. ...
Page 119
... When SOSC is selected to run from a digital clock input, rather than an external crystal (SOSCSRC = 0), 3: this bit has no effect. 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY The Clock Divider register features associated with Doze mode, as well as the postscaler for the FRC oscillator. ...
Page 120
... Note 1: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected. 2: When SOSC is selected to run from a digital clock input, rather than an external crystal (SOSCSRC = 0), 3: this bit has no effect. DS39995B-page 120 (2) (3) 2011 Microchip Technology Inc. ...
Page 121
... Unimplemented: Read as ‘0’ This bit is automatically cleared when the ROI bit is set and an interrupt occurs. Note 1: 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY R/W-1 R/W-0 R/W-0 (1) DOZE0 ...
Page 122
... DS39995B-page 122 U-0 U-0 — — R/W-0 R/W-0 (1) (1) (1) TUN4 TUN3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 R/W-0 (1) (1) (1) TUN2 TUN1 TUN0 bit Bit is unknown 2011 Microchip Technology Inc. ...
Page 123
... Perform the unlock sequence to allow a write to the OSCCON register low byte. 5. Set the OSWEN bit to initiate the oscillator switch. 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY Once the basic sequence is completed, the system clock hardware responds automatically, as follows: 1. The clock switching hardware compares the COSCx bits with the new value of the NOSCx bits ...
Page 124
... Sleep mode. Clearing the ROSEL bit allows the reference output frequency to change as the system clock changes during any clock switches. /2) available in OSC family devices can also be (Register 9-4). Setting the ROEN 2011 Microchip Technology Inc. ...
Page 125
... Base clock value divided by 2 0000 = Base clock value bit 7-0 Unimplemented: Read as ‘0’ The crystal oscillator must be enabled using the FOSC<2:0> bits; the crystal maintains the operation in Note 1: Sleep mode. 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY R/W-0 R/W-0 R/W-0 ROSEL RODIV3 ...
Page 126
... PIC24FV32KA304 FAMILY NOTES: DS39995B-page 126 2011 Microchip Technology Inc. ...
Page 127
... Put the device into IDLE mode BSET DSCON, #DSEN ; Enable Deep Sleep PWRSAV #SLEEP_MODE ; Put the device into Deep SLEEP mode 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY The assembly syntax of the PWRSAV instruction is shown in Example Note: SLEEP_MODE constants defined in the assembler comprehensive include file for the selected device ...
Page 128
... To set the DSEN bit, the unlock sequence in Example 10-2 is required: EXAMPLE 10-2: THE UNLOCK SEQUENCE //Disable Interrupts For 5 instructions asm volatile(“disi #5”); //Issue Unlock Sequence asm volatile mov #0x55, W0; mov W0, NVMKEY; mov #0xAA, W1; mov W1, NVMKEY; bset DSCON, #DSEN 2011 Microchip Technology Inc. CY ...
Page 129
... CORE plied in Deep Sleep mode, information in data RAM may be lost when exiting this mode. 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY Applications which require critical data to be saved prior to Deep Sleep may use the Deep Sleep General Purpose registers, DSGPR0 and DSGPR1 or data EEPROM (if available) ...
Page 130
... Read and clear the DPSLP status bit in RCON, and the DSWAKE status bits. 13. Read the DSGPRx registers (optional). 14. Once all state related configurations are complete, clear the RELEASE bit. 15. Application resumes normal operation. Power-on Resets ( ) PORs described in Section 10.2.4.7 Summary of Deep Sleep Sequence 2011 Microchip Technology Inc. ...
Page 131
... All register bits are reset only in the case of a POR event outside of Deep Sleep mode. Note 1: Unlike all other events, a Deep Sleep BOR event will NOT cause a wake-up from Deep Sleep; this re-arms 2: POR. 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY (1) U-0 U-0 U-0 — ...
Page 132
... DS39995B-page 132 U-0 U-0 U-0 — — — R/W-0, HS R/W-0, HS R/W-0, HS DSWDT DSRTCC DSMCLR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2,3) (1) U-0 R/W-0, HS — DSINT0 bit 8 U-0 R/W-0, HS (2,3) — DSPOR bit Bit is unknown 2011 Microchip Technology Inc. ...
Page 133
... Sleep mode, the ULPWUIF bit (IFS5<0>) is set. Soft- ware can check this bit upon wake-up to determine the wake-up source. See Example 10-3 for initializing the ULPWU module 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY EXAMPLE 10-3: / /******************************* // 1. Charge the capacitor on RB0 //******************************* TRISBbits.TRISB0 = 0 ...
Page 134
... Unimplemented: Read as ‘0’ DS39995B-page 134 (1) U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2011 Microchip Technology Inc. U-0 R/W-0 — ULPSINK bit 8 U-0 U-0 — — bit Bit is unknown ...
Page 135
... HVREG is still providing the regulated voltage at full supply current. This mode consumes the most power in Sleep, but provides the fastest wake-up from Sleep. 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY 10.4.3 SLEEP (STANDBY) MODE In Sleep mode, the device is in Sleep and the main HVREG is providing a regulated voltage at a reduced (standby) supply current ...
Page 136
... HVREG is off during Sleep 0 Sleep LVREG is enabled and provides Sleep voltage regulation Fast Wake-up HVREG mode (normal) is unchanged during Sleep 1 Sleep LVREG is disabled at all times Sleep HVREG goes to Low-Power Standby mode during 0 Sleep (Standby) LVREG is disabled at all times Description 2011 Microchip Technology Inc. ...
Page 137
... CPU Idles, waiting for something to invoke an interrupt routine. Enabling the automatic return to full-speed CPU operation on interrupts is enabled by setting the ROI bit (CLKDIV<15>). By default, interrupt events have no effect on Doze mode operation. 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY 10.6 Selective Peripheral Module Control ...
Page 138
... PIC24FV32KA304 FAMILY NOTES: DS39995B-page 138 2011 Microchip Technology Inc. ...
Page 139
... CK WR PORT Data Latch Read LAT Read PORT 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled ...
Page 140
... U-0 U-0 U-0 — — — U-0 R/W-1 R/W-1 — ANSA3 ANSA2 HSC = Hardware Settable/Clearable bit ‘0’ = Bit is cleared Register 11-1 to Register 11-3 U-0 U-0 — — bit 8 R/W-1 R/W-1 ANSA1 ANSA0 bit Bit is unknown 2011 Microchip Technology Inc. ...
Page 141
... Unimplemented: Read as ‘0’ bit 2-0 ANSC<2:0>: Analog Select Control bits 1 = Digital Input Buffer Not Active (Use for Analog Input Digital Input Buffer Active Not available on 20-pin or 28-pin devices. Note 1: 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY R/W-1 U-0 U-0 ANSB12 — ...
Page 142
... Make sure that there is no external pull-up source/pull-down sink when the internal pull-ups/pull-downs are enabled. Pull-ups and pull-downs on change notifi- Note: cation pins should always be disabled whenever the port pin is configured as a digital output. 2011 Microchip Technology Inc. , enable DD , enable ...
Page 143
... TIMER1 MODULE BLOCK DIAGRAM SOSCO/ T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY Figure 12-1 illustrates a block diagram of the 16-bit Timer1 module. To configure Timer1 for operation: 1. Set the TON bit (= 1). 2. Select the timer prescaler ratio using the TCKPS< ...
Page 144
... DS39995B-page 144 U-0 U-0 — — R/W-0 U-0 R/W-0 TCKPS0 — TSYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) /2) U-0 R/W-0 R/W-0 (1) (1) — T1ECS1 T1ECS0 bit 8 R/W-0 U-0 TCS — bit Bit is unknown 2011 Microchip Technology Inc. ...
Page 145
... T4CON control bits are used for setup and or Timer4 control. Timer2 inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 or Timer5 interrupt flags. 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY To configure Timer2/3 or Timer4/5 for 32-bit operation: 1. Set the T32 bit (T2CON<3> or T4CON<3> = 1). 2. ...
Page 146
... The ADC event trigger is available only on Timer2/3 in 32-bit mode and Timer3 in 16-bit mode. 2: DS39995B-page 146 Gate Sync PR3 PR2 (PR5) (PR4) Comparator LSB TMR2 TMR3 (TMR4) (TMR5) 16 (1) ( TMR3HLD (TMR5HLD) TCKPS<1:0> 2 TON 1x Prescaler 1, 8, 64, 256 01 00 TGATE TCS Sync 2011 Microchip Technology Inc. ...
Page 147
... Equal FIGURE 13-3: TIMER3 AND TIMER5 (16-BIT ASYNCHRONOUS) BLOCK DIAGRAM T3CK (T5CK) TGATE Set T3IF (T5IF Reset (1) ADC Event Trigger Equal The ADC event trigger is available only on Timer3. Note 1: 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY 1x Gate Sync TMR2 (TMR4) Sync ...
Page 148
... DS39995B-page 148 U-0 U-0 — — R/W-0 R/W-0 (1) TCKPS0 T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) /2) U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 — TCS — bit Bit is unknown 2011 Microchip Technology Inc. ...
Page 149
... External clock from the T3CK pin (on the rising edge Internal clock (F OSC bit 0 Unimplemented: Read as ‘0’ When 32-bit operation is enabled (TxCON<3> = 1), these bits have no effect on Timery operation. All timer Note 1: functions are set through TxCON. 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY U-0 U-0 (1) — — R/W-0 ...
Page 150
... PIC24FV32KA304 FAMILY NOTES: DS39995B-page 150 2011 Microchip Technology Inc. ...
Page 151
... Clock IC Clock Select Sources Trigger and Sync Logic Reset Trigger and Sync Sources 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY 14.1 General Operating Modes 14.1.1 SYNCHRONOUS AND TRIGGER MODES By default, the input capture module operates in a comprehensive free-running mode. The internal 16-bit counter, ...
Page 152
... ICyBUF for the msw). At least one capture value is available in the FIFO buffer when the odd module’s ICBNE bit (ICxCON1<3>) becomes set. Continue to read the buffer registers until ICBNE is cleared (performed automatically by hardware). IC32 bits for both modules to configure Trigger or 2011 Microchip Technology Inc. ...
Page 153
... Simple Capture mode: capture on every falling edge 001 = Edge Detect Capture mode: capture on every edge (rising and falling); ICI<1:0 bits do not control interrupt generation for this mode 000 = Input capture module is turned off 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY R/W-0 R/W-0 ...
Page 154
... DS39995B-page 154 U-0 U-0 — — R/W-0 R/W-1 SYNCSEL4 SYNCSEL3 SYNCSEL2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) (1) U-0 U-0 R/W-0 — — IC32 bit 8 R/W-1 R/W-0 R/W-1 SYNCSEL1 SYNCSEL0 bit Bit is unknown 2011 Microchip Technology Inc. ...
Page 155
... Compare or PWM events are generated each time a match between the internal counter and one of the Period registers occurs. 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY In Synchronous mode, the module begins performing its compare or PWM operation as soon as its selected clock source is enabled. Whenever an event occurs on the selected sync source, the module’ ...
Page 156
... Sync Logic Reset DS39995B-page 156 OCxCON1 OCxCON2 OCxR Match Event Comparator OCxTMR Reset Match Event Comparator OCxRS DCBx OCMx OCINV OCTRIS FLTOUT FLTTRIEN FLTMD ENFLTx OCFLTx OCx Pin OC Output and Fault Logic OCFA/ OCFB/ CxOUT OCx Interrupt 2011 Microchip Technology Inc. ...
Page 157
... Trigger mode operation starts after a trigger source event occurs. 6. Set the OCM<2:0> bits for the appropriate compare operation (‘0xx’). 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY For 32-bit cascaded operation, these steps are also necessary: 1. Set ...
Page 158
... OCxR and DCB<1:0> Buffers Comparator Match Event OC Output Timing OCxTMR Rollover Comparator Match Event OCxRS Buffer Rollover/Reset OCxRS a clock source by writing the OCMx OCINV OCTRIS FLTOUT FLTTRIEN FLTMD ENFLTx OCFLTx DCB<1:0> OCx Pin and Fault Logic OCFA/OCFB/CxOUT OCx Interrupt 2011 Microchip Technology Inc. ...
Page 159
... Note 1: Based Doze mode and PLL are disabled. CY OSC 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY 15.3.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the OCxRS and OCxR registers. The OCxRS and OCxR registers can be written to at any time, but the duty cycle value is not latched until a period is complete ...
Page 160
... Hz 122 Hz 977 FFFFh 7FFFh 0FFFh 244 Hz 488 Hz 3.9 kHz FFFFh 7FFFh 0FFFh ( MHz) CY 3.9 kHz 31.3 kHz 125 kHz 03FFh 007Fh 001Fh ( MHz) CY 15.6 kHz 125 kHz 500 kHz 03FFh 007Fh 001Fh 2011 Microchip Technology Inc. ...
Page 161
... TRIGSTAT (OCxCON2<6>) is cleared when OCxRS = OCxTMR or in software 0 = TRIGSTAT is only cleared by software The comparator module used for Fault input varies with the OCx module. OC1 and OC2 use Note 1: Comparator 1; OC3 and OC4 use Comparator 2; OC5 uses Comparator 3. 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY R/W-0 R/W-0 R/W-0 ...
Page 162
... Single Compare Single-Shot mode: initialize OCx pin low, compare event forces the OCx pin high 000 = Output compare channel is disabled The comparator module used for Fault input varies with the OCx module. OC1 and OC2 use Note 1: Comparator 1; OC3 and OC4 use Comparator 2; OC5 uses Comparator 3. DS39995B-page 162 (1) 2011 Microchip Technology Inc. ...
Page 163
... SYNCSEL setting. Use these inputs as trigger sources only and never as sync sources. 2: These bits affect the rising edge when OCINV = 1. The bits have no effect when the OCM bits 3: (OCxCON1<2:0>) = 001. 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY R/W-0 U-0 R/W-0 (3) OCINV — ...
Page 164
... Use these inputs as trigger sources only and never as sync sources. 2: These bits affect the rising edge when OCINV = 1. The bits have no effect when the OCM bits 3: (OCxCON1<2:0>) = 001. DS39995B-page 164 (1) (2) (2) (2) (2) (2) (2) (2) (2) (1) (1) (1) (1) (1) 2011 Microchip Technology Inc. ...
Page 165
... SPIx. Special Function Registers (SFRs) will follow a similar notation. For example, SPI1CON1 or SPI1CON2 refers to the control register for the SPI1 module. 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY To set up the SPI1 module for the Standard Master mode of operation using interrupts: ...
Page 166
... Control Control Clock SDO1 bit 0 SDI1 SPI1SR Transfer SPI1BUF Read SPI1BUF DS39995B-page 166 1:1 to 1:8 Secondary Prescaler Select Edge Shift Control Transfer Write SPI1BUF 16 Internal Data Bus 1:1/4/16/64 Primary F CY Prescaler SPI1CON1<1:0> SPI1CON1<4:2> Enable Master Clock 2011 Microchip Technology Inc. ...
Page 167
... SDO1 bit 0 SDI1 SPI1SR Transfer 8-Level FIFO Receive Buffer SPI1BUF Read SPI1BUF 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY To set up the SPI1 module for the Enhanced Buffer Slave mode of operation: 1. Clear the SPI1BUF register using interrupts: a) Clear the respective SPI1IF bit in the IFS0 register ...
Page 168
... R/W-0 SISEL2 SISEL1 SISEL0 HS = Hardware Settable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R-0, HSC R-0, HSC SPIBEC1 SPIBEC0 bit 8 R-0, HSC R-0, HSC SPITBF SPIRBF bit 0 HSC = Hardware Settable/Clearable bit x = Bit is unknown 2011 Microchip Technology Inc. ...
Page 169
... Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB. In Enhanced Buffer mode: Automatically set in hardware when SPIx transfers data from SPIxSR to buffer, filling the last unread buffer location. Automatically cleared in hardware when a buffer location is available for a transfer from SPIxSR. 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY DS39995B-page 169 ...
Page 170
... SPI modes (FRMEN = 1). DS39995B-page 170 R/W-0 R/W-0 R/W-0 DISSCK DISSDO MODE16 R/W-0 R/W-0 R/W-0 SPRE2 SPRE1 SPRE0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 (1) SMP CKE bit 8 R/W-0 R/W-0 PPRE1 PPRE0 bit Bit is unknown 2011 Microchip Technology Inc. ...
Page 171
... Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 SPIBEN: Enhanced Buffer Enable bit 1 = Enhanced buffer is enabled 0 = Enhanced buffer is disabled (Legacy mode) 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY U-0 U-0 U-0 — — ...
Page 172
... Microchip Technology Inc. ...
Page 173
... Pin assignment is controlled by the I2C1SEL Configuration bit. Programming this bit (= 0) multiplexes the module to the SCL1 and SDA1 pins. 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY 17.2 Communicating as a Master in a Single Master Environment The details of sending a message in Master mode depends on the communications protocol for the device being communicated with ...
Page 174
... Bit Detect Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2C1TRN LSB Reload Control Internal Data Bus Read Write I2C1MSK Read Write Read Write I2C1STAT Read Write I2C1CON Read Write Read Write I2C1BRG Read 2011 Microchip Technology Inc. ...
Page 175
... Note 1: Address will be Acknowledged only if GCEN = 1. 2: Match on this address can only occur on the upper byte in 10-Bit Addressing mode. 3: 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY 17.4 Slave Address Masking The I2C1MSK register address bit positions as “don’t care” for both 7-Bit and 10-Bit Addressing modes ...
Page 176
... R/W-0, HC ACKEN RCEN PEN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2 C™ pins are controlled by port functions 2 C slave slave slave) R/W-0 R/W-0 DISSLW SMEN bit 8 R/W-0, HC R/W-0, HC RSEN SEN bit Bit is unknown 2011 Microchip Technology Inc. ...
Page 177
... Repeated Start condition is not in progress bit 0 SEN: Start Condition Enable bit (when operating Initiates Start condition on SDAx and SCLx pins; hardware is clear at end of master Start sequence 0 = Start condition is not in progress 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY 2 C master; applicable during master receive) 2 ...
Page 178
... Bit is cleared nd byte of matched 10-bit address; hardware is clear at Stop detection slave) R-0, HSC R-0, HSC GCSTAT ADD10 bit 8 R-0, HSC R-0, HSC RBF TBF bit 0 HSC = Hardware Settable/Clearable bit x = Bit is unknown 2 C module is busy 2011 Microchip Technology Inc. ...
Page 179
... Hardware is set when I2C1RCV is written with received byte; hardware is clear when software reads I2C1RCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit is in progress, I2CxTRN is full 0 = Transmit is complete, I2CxTRN is empty Hardware is set when software writes to I2C1TRN; hardware is clear at completion of data transmission. 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY 2 C slave device address byte. ...
Page 180
... U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 AMSK9 AMSK8 bit 8 R/W-0 R/W-0 AMSK1 AMSK0 bit Bit is unknown U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown 2011 Microchip Technology Inc. ...
Page 181
... UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator IrDA Hardware Flow Control UARTx Receiver UARTx Transmitter 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY • Fully Integrated Baud Rate Generator (IBRG) with 16-bit Prescaler • Baud Rates Ranging from 1 Mbps to 15 bps at 16 MIPS • ...
Page 182
... BRG timer to be reset (cleared). This ensures the BRG does not wait for a timer overflow before generating the new baud rate. /(16 * 65536). shows the formula for computation of UART BAUD RATE WITH (1) BRGH = • (UxBRG + – • Baud Rate = F /2; Doze mode CY OSC /4 CY (1) 2011 Microchip Technology Inc. ...
Page 183
... Write ‘55h’ to UxTXREG – loads the Sync character into the transmit FIFO. 5. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits. 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY 18.5 Receiving in 8-Bit or 9-Bit Data Mode 1. ...
Page 184
... U-0 (1) IREN RTSMD — R/W-0 R/W-0 R/W-0 RXINV BRGH PDSEL1 HC = Hardware Clearable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) (2) (2) R/W-0 R/W-0 UEN1 UEN0 bit 8 R/W-0 R/W-0 PDSEL0 STSEL bit Bit is unknown 2011 Microchip Technology Inc. ...
Page 185
... STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit This feature is is only available for the 16x BRG mode (BRGH = 0). Note 1: Bit availability depends on pin availability. 2: 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY DS39995B-page 185 ...
Page 186
... R-1, HSC R-0, HSC R-0, HSC RIDLE PERR FERR HSC = Hardware Settable/Clearable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R-0, HSC R-1, HSC UTXBF TRMT bit 8 R/C-0, HS R-0, HSC OERR URXDA bit Bit is unknown 2011 Microchip Technology Inc. ...
Page 187
... Receive buffer has not overflowed (clearing a previously set OERR bit (1 0 transition) will reset the receiver buffer and the RSR to the empty state) bit 0 URXDA: Receive Buffer Data Available bit (read-only Receive buffer has data; at least one more character can be read 0 = Receive buffer is empty 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY DS39995B-page 187 ...
Page 188
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-x W-x — UTX8 bit 8 W-x W-x UTX1 UTX0 bit Bit is unknown U-0 R-0, HSC — URX8 bit 8 R-0, HSC R-0, HSC URX1 URX0 bit Bit is unknown 2011 Microchip Technology Inc. ...
Page 189
... Alarm Event Comparator Alarm Registers with Masks Repeat Counter 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY • BCD format for smaller software overhead • Optimized for long term battery operation • User calibration of the 32.768 kHz clock crystal/32K INTRC frequency with periodic auto-adjust • ...
Page 190
... RTCC using the RTCCSEL<1:0> bits secondary oscillator LPRC external clock, and external clock. ALRMVAL REGISTER MAPPING Alarm Value Register Window ALRMVAL<15:8> ALRMVAL<7:0> ALRMMIN ALRMSEC ALRMWD ALRMHR ALRMMNTH ALRMDAY PWCSTAB PWCSAMP 19-1). Example 19-1. 2011 Microchip Technology Inc. ...
Page 191
... The RCFGCAL register is only affected by a POR. Note 1: A write to the RTCEN bit is only allowed when RTCWREN = 1. 2: This bit is read-only cleared to ‘0’ write to the lower half of the MINSEC register. 3: 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY R-0, HSC R-0, HSC R/W-0 (3) ...
Page 192
... Maximum negative adjustment; subtracts 512 RTC clock pulses every one minute The RCFGCAL register is only affected by a POR. Note 1: A write to the RTCEN bit is only allowed when RTCWREN = 1. 2: This bit is read-only cleared to ‘0’ write to the lower half of the MINSEC register. 3: DS39995B-page 192 (1) (CONTINUED) 2011 Microchip Technology Inc. ...
Page 193
... Unimplemented: Read as ‘0’ The RTCPWC register is only affected by a POR. Note 1: When a new value is written to these register bits, the Seconds Value register should also be written to 2: properly reset the clock prescalers in the RTCC. 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY (1) R/W-0 R/W-0 R/W-0 ...
Page 194
... R/W-0 R/W-0 R/W-0 AMASK2 AMASK1 AMASK0 R/W-0 R/W-0 R/W-0 ARPT4 ARPT3 ARPT2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared th , once every 4 years) R/W-0 R/W-0 ALRMPTR1 ALRMPTR0 bit 8 R/W-0 R/W-0 ARPT1 ARPT0 bit Bit is unknown 2011 Microchip Technology Inc. ...
Page 195
... DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit bits Contains a value from bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits Contains a value from write to this register is only allowed when RTCWREN = 1. Note 1: 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY (1) U-0 U-0 U-0 — ...
Page 196
... SECTEN0 SECONE3 SECONE2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-x R/W-x WDAY1 WDAY0 bit 8 R/W-x R/W-x HRONE1 HRONE0 bit Bit is unknown R/W-x R/W-x MINONE1 MINONE0 bit 8 R/W-x R/W-x SECONE1 SECONE0 bit Bit is unknown 2011 Microchip Technology Inc. ...
Page 197
... HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits Contains a value from bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits Contains a value from write to this register is only allowed when RTCWREN = 1. Note 1: 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY R/W-x R/W-x R/W-x MTHTEN0 MTHONE3 ...
Page 198
... Contains a value from DS39995B-page 198 R/W-x R/W-x R/W-x MINTEN0 MINONE3 MINONE2 R/W-x R/W-x R/W-x SECTEN0 SECONE3 SECONE2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-x R/W-x MINONE1 MINONE0 bit 8 R/W-x R/W-x SECONE1 SECONE0 bit Bit is unknown 2011 Microchip Technology Inc. ...
Page 199
... The sample window timer starts counting at the end of the stability window when PWCEN = 1. If PWCSTAB<7:0> the sample window timer starts counting from every alarm event when PWCEN = 1. Writes to this register are only allowed when RTCWREN = 1. Note 1: 2011 Microchip Technology Inc. PIC24FV32KA304 FAMILY R/W-x R/W-x R/W-x ...
Page 200
... To avoid a false alarm event, the timer and alarm values should only be changed while the alarm is disabled (ALRMEN = 0 recommended that the ALCFGRPT register and CHIME bit be changed when RTCSYNC = 0. 2011 Microchip Technology Inc. ...