PIC24F16KA301-E/SO Microchip Technology, PIC24F16KA301-E/SO Datasheet - Page 173

• Manufacturer Part Number: PIC24F16KA301-E/SO
• Description: 16KB Flash, 2KB RAM, 512B EEPROM, 16 MIPS, 12-bit ADC, CTMU, XLP 20 SOIC .300in
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24F16KA301-E/SO

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 16KB (5.5K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SOIC (0.295", 7.50mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

17.0
The Inter-Integrated Circuit (I
interface
peripheral or microcontroller devices. These peripheral
devices may be serial data EEPROMs, display drivers,
A/D Converters, etc.
The I
• Independent master and slave logic
• 7-bit and 10-bit device addresses
• General call address, as defined in the I
• Clock stretching to provide delays for the
• Both 100 kHz and 400 kHz bus specifications
• Configurable address masking
• Multi-Master modes to prevent loss of messages
• Bus Repeater mode, allowing the acceptance of
• Automatic SCL
A block diagram of the module is shown in
17.1
The I
with peripheral multiplexing, the I2C1 module, in 28-pin
devices, can be reassigned to the alternate pins. These
alternate pins are designated as SCL1 and SDA1
during device configuration.
Pin assignment
Configuration bit. Programming this bit (= 0) multiplexes
the module to the SCL1 and SDA1 pins.
 2011 Microchip Technology Inc.
Note:
processor to respond to a slave data request
in arbitration
all messages as a slave, regardless of the
address
2
2
C module supports these features:
C module is tied to a fixed pin. To allow flexibility
INTER-INTEGRATED
CIRCUIT™ (I
Pin Remapping Options
useful
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended
reference source. For more information
on the Inter-Integrated Circuit, refer to the
“PIC24F
Section 24. “Inter-Integrated Circuit™
(I
2
C™)” (DS39702).
is controlled by the I2C1SEL
for
Family
to
communicating
2
C™)
be
2
C™) module is a serial
Reference
a
comprehensive
2
C protocol
Figure
with
Manual”,
other
17-1.
PIC24FV32KA304 FAMILY
17.2
The details of sending a message in Master mode
depends on the communications protocol for the device
being communicated with. Typically, the sequence of
events is as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Wait for and verify an Acknowledge from the
11. Enable master reception to receive serial
12. Generate an ACK or NACK condition at the end
13. Generate a Stop condition on SDA1 and SCL1.
Assert a Start condition on SDA1 and SCL1.
Send the I
with a write indication.
Wait for and verify an Acknowledge from the
slave.
Send the first data byte (sometimes known as
the command) to the slave.
Wait for and verify an Acknowledge from the
slave.
Send the serial memory address low byte to the
slave.
Repeat Steps 4 and 5 until all data bytes are
sent.
Assert a Repeated Start condition on SDA1 and
SCL1.
Send the device address byte to the slave with
a read indication.
slave.
memory data.
of a received byte of data.
Communicating as a Master in a
Single Master Environment
2
C device address byte to the slave
DS39995B-page 173