PIC24F16KA302T-I/ML Microchip Technology, PIC24F16KA302T-I/ML Datasheet - Page 165

• Manufacturer Part Number: PIC24F16KA302T-I/ML
• Description: 16KB Flash, 2KB RAM, 512B EEPROM, 16 MIPS, 12-bit ADC, CTMU, XLP 28 QFN 6x6mm T/
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24F16KA302T-I/ML

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (5.5K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16.0
The Serial Peripheral Interface (SPI) module is a
synchronous serial interface useful for communicating
with other peripheral or microcontroller devices. These
peripheral devices may be serial data EEPROMs, shift
registers, display drivers, A/D Converters, etc. The SPI
module is compatible with Motorola
interfaces.
The module supports operation in two buffer modes. In
Standard mode, data is shifted through a single serial
buffer. In Enhanced Buffer mode, data is shifted
through an 8-level FIFO buffer.
The module also supports a basic framed SPI protocol
while operating in either Master or Slave mode. A total
of four framed SPI configurations are supported.
The SPI serial interface consists of four pins:
• SDI1: Serial Data Input
• SDO1: Serial Data Output
• SCK1: Shift Clock Input or Output
• SS1: Active-Low Slave Select or Frame
The SPI module can be configured to operate using 2,
3 or 4 pins. In the 3-pin mode, SS1 is not used. In the
2-pin mode, both SDO1 and SS1 are not used.
Block diagrams of the module in Standard and
Enhanced Buffer modes are shown in
Figure
The devices of the PIC24FV32KA304 family offer two
SPI modules on a device.
 2011 Microchip Technology Inc.
Note:
Note:
Synchronization I/O Pulse
Note:
16-2.
SERIAL PERIPHERAL
INTERFACE (SPI)
operations
instructions) on the SPI1BUF register in
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on the Serial
Peripheral Interface, refer to the “PIC24F
Family Reference Manual”, Section 23.
“Serial
(DS39699).
Do
either Standard or Enhanced Buffer mode.
In this section, the SPI modules are
referred to as SPIx. Special Function
Registers (SFRs) will follow a similar
notation. For example, SPI1CON1 or
SPI1CON2 refers to the control register
for the SPI1 module.
not
Peripheral
perform
(such
Interface
as
read-modify-write
®
Figure 16-1
SPI and SIOP
bit-oriented
(SPI)”
PIC24FV32KA304 FAMILY
and
To set up the SPI1 module for the Standard Master
mode of operation:
1.
2.
3.
4.
5.
To set up the SPI module for the Standard Slave mode
of operation:
1.
2.
3.
4.
5.
6.
7.
If using interrupts:
a)
b)
c)
Write the desired settings to the SPI1CON1 and
SPI1CON2 registers with the MSTEN bit
(SPI1CON1<5>) = 1.
Clear the SPIROV bit (SPI1STAT<6>).
Enable SPI operation by setting the SPIEN bit
(SPI1STAT<15>).
Write the data to be transmitted to the SPI1BUF
register. Transmission (and reception) will start
as soon as data is written to the SPI1BUF
register.
Clear the SPI1BUF register.
If using interrupts:
a)
b)
c)
Write the desired settings to the SPI1CON1
and SPI1CON2 registers with the MSTEN bit
(SPI1CON1<5>) = 0.
Clear the SMP bit.
If the CKE bit is set, then the SSEN bit
(SPI1CON1<7>) must be set to enable the SS1
pin.
Clear the SPIROV bit (SPI1STAT<6>).
Enable SPI operation by setting the SPIEN bit
(SPI1STAT<15>).
Clear the respective SPI1IF bit in the IFS0
register.
Set the respective SPI1IE bit in the IEC0
register.
Write the respective SPI1IPx bits in the
IPC2 register to set the interrupt priority.
Clear the respective SPI1IF bit in the IFS0
register.
Set the respective SPI1IE bit in the IEC0
register.
Write the respective SPI1IP bits in the IPC2
register to set the interrupt priority.
DS39995B-page 165