PIC24F16KA302T-I/SO Microchip Technology, PIC24F16KA302T-I/SO Datasheet - Page 160

• Manufacturer Part Number: PIC24F16KA302T-I/SO
• Description: 16KB Flash, 2KB RAM, 512B EEPROM, 16 MIPS, 12-bit ADC, CTMU, XLP 28 SOIC .300in
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24F16KA302T-I/SO

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (5.5K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (0.295", 7.50mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FV32KA304 FAMILY
15.4
The DCB bits (OCxCON2<10:9>) provide for resolution
better than one instruction cycle. When used, they
delay the falling edge generated from a match event by
a portion of an instruction cycle.
For example, setting DCB<1:0> = 10 causes the falling
edge to occur halfway through the instruction cycle in
which the match event occurs, instead of at the
beginning.
OCM<2:0> = 001. When operating the module in PWM
mode (OCM<2:0> = 110 or 111), the DCB bits will be
double-buffered.
TABLE 15-1:
TABLE 15-2:
DS39995B-page 160
Prescaler Ratio
Period Value
Resolution (bits)
Note 1:
Prescaler Ratio
Period Value
Resolution (bits)
Note 1:
PWM Frequency
PWM Frequency
Subcycle Resolution
Based on F
Based on F
These
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (F
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (F
bits
CY
CY
= F
= F
cannot
OSC
OSC
30.5 Hz
FFFFh
/2; Doze mode and PLL are disabled.
FFFFh
/2; Doze mode and PLL are disabled.
7.6 Hz
16
16
8
8
be
used
244 Hz
FFFFh
FFFFh
61 Hz
16
16
1
1
when
122 Hz
488 Hz
7FFFh
7FFFh
15
15
1
1
The DCB bits are intended for use with a clock source
identical to the system clock. When an OCx module
with enabled prescaler is used, the falling edge delay
caused by the DCB bits will be referenced to the
system clock period rather than the OCx module’s
period.
3.9 kHz
977 Hz
0FFFh
0FFFh
12
12
1
1
15.6 kHz
3.9 kHz
03FFh
03FFh
10
10
1
1
 2011 Microchip Technology Inc.
31.3 kHz
125 kHz
007Fh
007Fh
CY
1
7
CY
1
7
= 4 MHz)
= 16 MHz)
125 kHz
500 kHz
001Fh
001Fh
(1)
1
5
1
5
(1)