PIC24F32KA301T-I/SS Microchip Technology, PIC24F32KA301T-I/SS Datasheet - Page 129

• Manufacturer Part Number: PIC24F32KA301T-I/SS
• Description: 32KB Flash, 2KB RAM, 512B EEPROM, 16 MIPS, 12-bit ADC, CTMU, XLP 20 SSOP .209in
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24F32KA301T-I/SS

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 32KB (11K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP (0.209", 5.30mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.2.4.2
Deep Sleep mode exits on any one of the following events:
• POR event on V
• DSWDT time-out. When the DSWDT timer times
• RTCC alarm (if RTCEN = 1).
• Assertion (‘0’) of the MCLR pin.
• Assertion of the INT0 pin (if the interrupt was
Exiting Deep Sleep mode generally does not retain the
state of the device and is equivalent to a Power-on
Reset (POR) of the device. Exceptions to this include
the RTCC (if present), which remains operational
through the wake-up, the DSGPRx registers and
DSWDT.
Wake-up events that occur after Deep Sleep exits but
before the POR sequence completes are ignored and
are not be captured in the DSWAKE register.
The sequence for exiting Deep Sleep mode is:
1.
2.
3.
4.
5.
6.
10.2.4.3
As exiting Deep Sleep mode causes a POR, most
Special Function Registers reset to their default POR
values. In addition, because V
plied in Deep Sleep mode, information in data RAM
may be lost when exiting this mode.
 2011 Microchip Technology Inc.
circuit to re-arm the V
external V
natural arming voltage of the POR circuit.
out, the device exits Deep Sleep.
enabled before Deep Sleep mode was entered).
The polarity configuration is used to determine the
assertion level (‘0’ or ‘1’) of the pin that will cause
an exit from Deep Sleep mode. Exiting from Deep
Sleep mode requires a change on the INT0 pin
while in Deep Sleep mode.
Note:
After a wake-up event, the device exits Deep
Sleep and performs a POR. The DSEN bit is
cleared automatically. Code execution resumes
at the Reset vector.
To determine if the device exited Deep Sleep,
read the Deep Sleep bit, DPSLP (RCON<10>).
This bit will be set if there was an exit from Deep
Sleep mode. If the bit is set, clear it.
Determine the wake-up source by reading the
DSWAKE register.
Determine if a DSBOR event occurred during
Deep Sleep mode by reading the DSBOR bit
(DSCON<1>).
If application context data has been saved, read
it back from the DSGPR0 and DSGPR1
registers.
Clear the RELEASE bit (DSCON<0>).
Any interrupt pending when entering
Deep Sleep mode is cleared.
DD
Exiting Deep Sleep Mode
Saving Context Data with the
DSGPR0/DSGPR1 Registers
supply must be lowered to the
DD
supply. If there is no DSBOR
DD
supply POR circuit, the
CORE
power is not sup-
PIC24FV32KA304 FAMILY
Applications which require critical data to be saved
prior to Deep Sleep may use the Deep Sleep General
Purpose registers, DSGPR0 and DSGPR1 or data
EEPROM (if available). Unlike other SFRs, the
contents of these registers are preserved while the
device is in Deep Sleep mode. After exiting Deep
Sleep, software can restore the data by reading the
registers and clearing the RELEASE bit (DSCON<0>).
10.2.4.4
During Deep Sleep, the general purpose I/O pins retain
their previous states and the Secondary Oscillator
(SOSC) will remain running, if enabled. Pins that are
configured as inputs (TRISx bit set), prior to entry into
Deep Sleep, remain high-impedance during Deep
Sleep. Pins that are configured as outputs (TRISx bit
clear), prior to entry into Deep Sleep, remain as output
pins during Deep Sleep. While in this mode, they
continue to drive the output level determined by their
corresponding LATx bit at the time of entry into Deep
Sleep.
Once the device wakes back up, all I/O pins continue to
maintain their previous states, even after the device
has finished the POR sequence and is executing
application code again. Pins configured as inputs
during Deep Sleep remain high-impedance and pins
configured as outputs continue to drive their previous
value. After waking up, the TRIS and LAT registers,
and the SOSCEN bit (OSCCON<1>) are reset. If
firmware modifies any of these bits or registers, the I/O
will not immediately go to the newly configured states.
Once
(DSCON<0>), the I/O pins are “released”. This causes
the I/O pins to take the states configured by their
respective TRIS and LAT bit values.
This means that keeping the SOSC running after
waking up requires the SOSCEN bit to be set before
clearing RELEASE.
If the Deep Sleep BOR (DSBOR) is enabled, and a
DSBOR or a true POR event occurs during Deep
Sleep, the I/O pins will be immediately released, similar
to clearing the RELEASE bit. All previous state
information will be lost, including the general purpose
DSGPR0 and DSGPR1 contents.
If a MCLR Reset event occurs during Deep Sleep, the
DSGPRx, DSCON and DSWAKE registers will remain
valid, and the RELEASE bit will remain set. The state
of the SOSC will also be retained. The I/O pins,
however, will be reset to their MCLR Reset state. Since
RELEASE is still set, changes to the SOSCEN bit
(OSCCON<1>) cannot take effect until the RELEASE
bit is cleared.
In all other Deep Sleep wake-up cases, application
firmware must clear the RELEASE bit in order to
reconfigure the I/O pins.
the
I/O Pins During Deep Sleep
firmware
clears
the
DS39995B-page 129
RELEASE
bit