PIC24F32KA302-E/SP Microchip Technology, PIC24F32KA302-E/SP Datasheet - Page 205

• Manufacturer Part Number: PIC24F32KA302-E/SP
• Description: 32KB Flash, 2KB RAM, 512B EEPROM, 16 MIPS, 12-bit ADC, CTMU, XLP 28 SPDIP .300in
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24F32KA302-E/SP

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (11K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

20.1.3
The LENDIAN bit (CRCCON1<3>) is used to control
the shift direction. By default, the CRC will shift data
through the engine, MSb first. Setting LENDIAN (= 1)
causes the CRC to shift data, LSb first. This setting
allows better integration with various communication
schemes and removes the overhead of reversing the
bit order in software. Note that this only changes the
direction of the data that is shifted into the engine. The
result of the CRC calculation will still be a normal CRC
result, not a reverse CRC result.
20.1.4
The module generates an interrupt that is configurable
by the user for either of two conditions. If CRCISEL is
‘0’, an interrupt is generated when the VWORD<4:0>
bits make a transition from a value of ‘1’ to ‘0’. If
CRCISEL is ‘1’, an interrupt will be generated after the
CRC operation finishes and the module sets the
CRCGO bit to ‘0’. Manually setting CRCGO to ‘0’ will
not generate an interrupt.
20.1.5
To use the module for a typical CRC calculation:
1.
2.
3.
4.
5.
6.
7.
8.
 2011 Microchip Technology Inc.
Set the CRCEN bit to enable the module.
Configure the module for the desired operation:
a)
b)
c)
Preload the FIFO by writing to the CRCDATL
and CRCDATH registers until the CRCFUL bit is
set or no data is left.
Clear old results by writing 00h to CRCWDATL
and CRCWDATH. CRCWDAT can also be left
unchanged to resume a previously halted
calculation.
Set the CRCGO bit to start calculation.
Write remaining data into the FIFO as space
becomes available.
When the calculation completes, CRCGO is
automatically cleared. An interrupt will be
generated if CRCISEL = 1.
Read CRCWDATL and CRCWDATH for the
result of the calculation.
Program the desired polynomial using the
CRCXORL and CRCXORH registers, and
the PLEN<4:0> bits
Configure the data width and shift direction
using the DWIDTH and LENDIAN bits
Select the desired interrupt mode using the
CRCISEL bit
TYPICAL OPERATION
DATA SHIFT DIRECTION
INTERRUPT OPERATION
PIC24FV32KA304 FAMILY
20.2
There are eight registers associated with the module:
• CRCCON1
• CRCCON2
• CRCXORL
• CRCXORH
• CRCDATL
• CRCDATH
• CRCWDATL
• CRCWDATH
The CRCCON1 and CRCCON2 registers
and
and configure the various settings. The CRCXOR
registers
polynomial terms to be used in the CRC equation. The
CRCDAT and CRCWDAT registers are each register
pairs that serve as buffers for the double-word, input
data and CRC processed output, respectively.
Register
Registers
(Register 20-3
20-2) control the operation of the module,
and
Register
DS39995B-page 205
20-4) select the
(Register 20-1