PIC24FJ64GB002-I/SS Microchip Technology, PIC24FJ64GB002-I/SS Datasheet - Page 41

• Manufacturer Part Number: PIC24FJ64GB002-I/SS
• Description: 16-bit, 16 MIPS, 64KB Flash, 8KB RAM, Nanowatt XLP, USB OTG 28 SSOP .209in TUBE
• Manufacturer: Microchip Technology

Specifications of PIC24FJ64GB002-I/SS

• Processor Series: PIC24
• Core: PIC24F
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 8192 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-28
• Development Tools By Supplier: MPLAB Integrated Development Environment
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current (max): 300 mA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 4-9:
TABLE 4-10:
I2C1RCV
I2C1TRN
I2C1BRG
I2C1CON
I2C1STAT
I2C1ADD
I2C1MSK
I2C2RCV
I2C2TRN
I2C2BRG
I2C2CON
I2C2STAT
I2C2ADD
I2C2MSK
Legend:
U1MODE
U1STA
U1TXREG
U1RXREG
U1BRG
U2MODE
U2STA
U2TXREG
U2RXREG
U2BRG
Legend:
File Name
File Name
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Addr
0220
0222
0224
0226
0228
0230
0232
0234
0236
0238
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Addr
020A
020C
021A
021C
0200
0202
0204
0206
0208
0210
0212
0214
0216
0218
UTXISEL1 UTXINV UTXISEL0
UTXISEL1 UTXINV UTXISEL0
I
UART REGISTER MAPS
UARTEN
UARTEN
2
Bit 15
C™ REGISTER MAP
ACKSTAT TRSTAT
ACKSTAT TRSTAT
—
—
—
—
I2CEN
I2CEN
Bit 15
—
—
—
—
—
—
—
—
—
—
Bit 14
—
—
—
—
—
—
Bit 14
—
—
—
—
—
—
—
—
—
—
—
—
USIDL
USIDL
Bit 13
I2CSIDL SCLREL
I2CSIDL SCLREL
Bit 13
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bit 12
IREN
IREN
—
—
—
—
—
—
Bit 12
—
—
—
—
—
—
—
—
—
—
—
—
UTXBRK
UTXBRK
RTSMD
RTSMD
Bit 11
—
—
—
—
IPMIEN
IPMIEN
Bit 11
—
—
—
—
—
—
—
—
—
—
—
—
UTXEN
UTXEN
Bit 10
—
—
—
—
—
—
Bit 10
A10M
A10M
BCL
BCL
—
—
—
—
—
—
—
—
—
—
UTXBF
UTXBF
UEN1
UEN1
Bit 9
Baud Rate Generator Prescaler Register
Baud Rate Generator Prescaler Register
GCSTAT
GCSTAT
DISSLW
DISSLW
—
—
—
—
Bit 9
—
—
—
—
—
—
TRMT
TRMT
UEN0
UEN0
Bit 8
ADD10
ADD10
SMEN
SMEN
Bit 8
—
—
—
—
URXISEL1 URXISEL0
URXISEL1 URXISEL0
WAKE
WAKE
Bit 7
IWCOL
IWCOL
GCEN
GCEN
Bit 7
LPBACK
LPBACK
STREN
STREN
I2COV
I2COV
Bit 6
Bit 6
Address Mask Register
Address Mask Register
Baud Rate Generator Register
Baud Rate Generator Register
ADDEN
ADDEN
ACKDT
ACKDT
ABAUD
ABAUD
Address Register
Address Register
Bit 5
Bit 5
D/A
D/A
Transmit Register
Transmit Register
Receive Register
Receive Register
ACKEN
ACKEN
Transmit Register
Transmit Register
RXINV
RIDLE
RXINV
RIDLE
Receive Register
Receive Register
Bit 4
Bit 4
P
P
RCEN
RCEN
BRGH
PERR
BRGH
PERR
Bit 3
Bit 3
S
S
PDSEL1
PDSEL1
FERR
FERR
Bit 2
PEN
R/W
PEN
R/W
Bit 2
PDSEL0
PDSEL0
RSEN
RSEN
OERR
OERR
Bit 1
RBF
RBF
Bit 1
URXDA
URXDA
STSEL
STSEL
Bit 0
SEN
SEN
TBF
TBF
Bit 0
Resets
Resets
0000
0110
xxxx
0000
0000
0000
0110
xxxx
0000
0000
0000
00FF
0000
1000
0000
0000
0000
0000
00FF
0000
1000
0000
0000
0000
All
All