PIC24FV16KA304-E/PT Microchip Technology, PIC24FV16KA304-E/PT Datasheet - Page 79

• Manufacturer Part Number: PIC24FV16KA304-E/PT
• Description: 16KB Flash, 2KB RAM, 512B EEPROM, 16 MIPS, 12-bit ADC, CTMU, 5V 44 TQFP 10x10x1m
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FV16KA304-E/PT

• Processor Series: PIC24FV
• Core: PIC
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 16 KB
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-44
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 38
• Eeprom Size: 512 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / Rohs Status: Details

8.0
The PIC24F interrupt controller reduces the numerous
peripheral interrupt request signals to a single interrupt
request signal to the CPU. It has the following features:
• Up to eight processor exceptions and
• Seven user-selectable priority levels
• Interrupt Vector Table (IVT) with up to 118 vectors
• Unique vector for each interrupt or exception
• Fixed priority within a specified user priority level
• Alternate Interrupt Vector Table (AIVT) for debug
• Fixed interrupt entry and return latencies
8.1
The IVT is shown in
program memory, starting at location, 000004h. The
IVT contains 126 vectors, consisting of eight
non-maskable trap vectors, plus, up to 118 sources of
interrupt. In general, each interrupt source has its own
vector. Each interrupt vector contains a 24-bit wide
address. The value programmed into each interrupt
vector location is the starting address of the associated
Interrupt Service Routine (ISR).
Interrupt vectors are prioritized in terms of their natural
priority; this is linked to their position in the vector table.
All other things being equal, lower addresses have a
higher natural priority. For example, the interrupt
associated with vector 0 will take priority over interrupts
at any other vector address.
PIC24FV32KA304
non-maskable traps and unique interrupts; these are
summarized in
 2011 Microchip Technology Inc.
Note:
software traps
source
support
INTERRUPT CONTROLLER
Interrupt Vector (IVT) Table
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended
reference source. For more information
on the Interrupt Controller, refer to the
“PIC24F
Section 8. “Interrupts” (DS39707).
Table 8-1
Figure
family
Family
to
and
8-1. The IVT resides in the
be
Table
Reference
devices
a
8-2.
comprehensive
implement
Manual”,
PIC24FV32KA304 FAMILY
8.1.1
The Alternate Interrupt Vector Table (AIVT) is located
after the IVT, as shown in
AIVT
(INTCON2<15>). If the ALTIVT bit is set, all interrupt
and exception processes will use the alternate vectors
instead of the default vectors. The alternate vectors are
organized in the same manner as the default vectors.
The AIVT supports emulation and debugging efforts by
providing a means to switch between an application
and a support environment without requiring the
interrupt vectors to be reprogrammed. This feature also
enables switching between applications for evaluation
of different software algorithms at run-time. If the AIVT
is not needed, the AIVT should be programmed with
the same addresses used in the IVT.
8.2
A device Reset is not a true exception, because the
interrupt controller is not involved in the Reset process.
The PIC24F devices clear their registers in response to
a Reset, which forces the Program Counter (PC) to
zero. The microcontroller then begins program
execution at location, 000000h. The user programs a
GOTO instruction at the Reset address, which redirects
the program execution to the appropriate start-up
routine.
Note:
is
Reset Sequence
provided
ALTERNATE INTERRUPT VECTOR
TABLE (AIVT)
Any unimplemented or unused vector
locations in the IVT and AIVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESET instruction.
by
the
Figure
ALTIVT
8-1. Access to the
DS39995B-page 79
control
bit