PIC24FV32KA301T-I/SO Microchip Technology, PIC24FV32KA301T-I/SO Datasheet - Page 73

• Manufacturer Part Number: PIC24FV32KA301T-I/SO
• Description: 32KB Flash, 2KB RAM, 512B EEPROM, 16 MIPS, 12-bit ADC, CTMU, 5V 20 SOIC .300in T
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FV32KA301T-I/SO

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 32KB (11K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (0.295", 7.50mm Width)
• Processor Series: PIC24FV
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7.0
The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
• POR: Power-on Reset
• MCLR: Pin Reset
• SWR: RESET Instruction
• WDTR: Watchdog Timer Reset
• BOR: Brown-out Reset
• Low-Power BOR/Deep Sleep BOR
• TRAPR: Trap Conflict Reset
• IOPUWR: Illegal Opcode Reset
• UWR: Uninitialized W Register Reset
A simplified block diagram of the Reset module is
shown in
FIGURE 7-1:
 2011 Microchip Technology Inc.
Note:
RCON<SBOREN>
RESETS
Figure
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended
reference source. For more information
on Resets, refer to the “PIC24F Family
Reference Manual”, Section 40. “Reset
with Programmable Brown-out Reset”
(DS39728).
SLEEP
7-1.
0
1
BOREN<1:0>
RESET SYSTEM BLOCK DIAGRAM
to
00
01
10
11
be
MCLR
V
(PIC24FV32KA3XX only)
a
Enable Voltage Regulator
DD
Configuration Mismatch
Uninitialized W Register
comprehensive
Illegal Opcode
Trap Conflict
Sleep or Idle
Brown-out
V
RESET
Instruction
Module
Detect
DD
WDT
Reset
Rise
PIC24FV32KA304 FAMILY
Glitch Filter
Any active source of Reset will make the SYSRST
signal active. Many registers associated with the CPU
and peripherals are forced to a known Reset state.
Most registers are unaffected by a Reset; their status is
unknown on Power-on Reset (POR) and unchanged by
all other Resets.
All types of device Reset will set a corresponding status
bit in the RCON register to indicate the type of Reset
(see
the BOR and POR bits (RCON<1:0>) which are set.
The user may set or clear any bit at any time during
code execution. The RCON bits only serve as status
bits. Setting a particular Reset status bit in software will
not cause a device Reset to occur.
The RCON register also has other bits associated with
the Watchdog Timer (WDT) and device power-saving
states. The function of these bits is discussed in other
sections of this manual.
Note:
Note:
POR
BOR
Register
Refer to the specific peripheral or CPU
section of this manual for register Reset
states.
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
7-1). A POR will clear all bits except for
DS39995B-page 73
SYSRST