PIC24HJ64GP510AT-I/PT Microchip Technology, PIC24HJ64GP510AT-I/PT Datasheet - Page 158

16 Bit MCU 40MIPS 64KB FLASH 100 TQFP 12x12x1mm T/R

PIC24HJ64GP510AT-I/PT

Manufacturer Part Number
PIC24HJ64GP510AT-I/PT
Description
16 Bit MCU 40MIPS 64KB FLASH 100 TQFP 12x12x1mm T/R
Manufacturer
Microchip Technology
Series
PIC® 24Hr

Specifications of PIC24HJ64GP510AT-I/PT

Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
64KB (22K x 24)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC24HJ64GP510AT-I/PT
Manufacturer:
MICROCHIP
Quantity:
12 000
Part Number:
PIC24HJ64GP510AT-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC24HJXXXGPX06A/X08A/X10A
15.1
Configure the Output Compare modes by setting the
appropriate Output Compare Mode (OCM<2:0>) bits in
the Output Compare Control (OCxCON<2:0>) register.
Table 15-1 lists the different bit settings for the Output
Compare modes. Figure 15-2 illustrates the output
compare operation for various modes. The user
TABLE 15-1:
FIGURE 15-2:
DS70592B-page 158
OCM<2:0>
000
001
010
011
100
101
110
111
Active-High One-Shot
Active-Low One-Shot
(OCM = 110 or 111)
Delayed One-Shot
Continuous Pulse
Output Compare Modes
(OCM = 001)
(OCM = 010)
(OCM = 011)
(OCM = 100)
(OCM = 101)
Module Disabled
Active-Low One-Shot
Active-High One-Shot
Toggle
Delayed One-Shot
Continuous Pulse
PWM without Fault Protection
PWM with Fault Protection
OUTPUT COMPARE MODES
Toggle
TMRy
PWM
OUTPUT COMPARE OPERATION
OCxRS
OCxR
Mode
Output Compare
Mode Enabled
Current output is maintained
Controlled by GPIO register
Preliminary
‘1’, if OCxR is non-zero
‘1’, if OCxR is non-zero
OCx Pin Initial State
‘0’, if OCxR is zero
‘0’, if OCxR is zero
Timer is Reset on
Period Match
0
1
0
0
application must disable the associated timer when
writing to the Output Compare Control registers to
avoid malfunctions.
Note:
See Section 13. “Output Compare”
(DS70247) in the “dsPIC33F/PIC24H
Family Reference Manual” for OCxR and
OCxRS register restrictions.
OCx rising edge
OCx falling edge
OCx rising and falling edge
OCx falling edge
OCx falling edge
No interrupt
OCFA falling edge for OC1 to OC4
OCx Interrupt Generation
 2009 Microchip Technology Inc.

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