PIC32MX575F256LT-80I/PT Microchip Technology, PIC32MX575F256LT-80I/PT Datasheet - Page 2

• Manufacturer Part Number: PIC32MX575F256LT-80I/PT
• Description: 256KB Flash, 64KB RAM, 80 MHz, USB, 1xCAN, 8 DMA 100 TQFP 12x12x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX575F256LT-80I/PT

• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Additional Notes:
1. extern unsigned int EthPhyMIIMAddress(void):
2. extern unsigned int EthPhyMIIMClock(void):
3. extern eEthRes EthPhyConfigureMII(eEthPhyCfgFlags cFlags):
4. extern eEthRes EthPhyConfigureMdix(eEthOpenFlags oFlags):
1. All functions in the PHY library are defined as weak. You can
2. Take a look in the “..install path\Microchip
3. All functions needed to access the PHY MIIM registers are part of
replace any of the functions with your own implementation if need
arises. The function header in the “..install
path\Microchip\Include\TCPIP-BSD\eth_phy.h” explains what
input/output and behavior the respective function should have.
Solutions\Microchip\TCPIP-BSD\eth_phy\nat_dp83848c.c” or
“..install path\Microchip Solutions\Microchip\TCPIP-
BSD\eth_phy\smsc_8700.c” for an implementation example. Follow
the same approach.
the provided Ethernet library.
a. does not take parameters;
b. Should return the address the PHY responds to. Depends on
c. Can be inlined/#defined
a. does not take parameters;
b. Should return the maximum clock frequency that the PHY can
c. Can be inlined/#defined
a. This function should configure the PHY in one of MII/RMII
b. The relevant input flags are:
c. It should return:
a. The function should configure the MDIX mode for the PHY.
b. The relevant input flags are:
c. It should return:
the hardware design.
use for the MIIM transactions.
operation modes.
ii. National DP83848C supports 25 MHz, for example.
ii. ETH_PHY_CFG_MII if MII configuration is requested
ii. An error code if the requested configuration is not
ii. else ETH_OPEN_MDIX_NORM/ETH_OPEN_MDIX_SWAP for
ii. An error code if the requested mode is not supported.
i. Most PHY’s should support 2 MHz.
i. ETH_PHY_CFG_RMII if RMII configuration is requested
i. ETH_RES_OK for success
i. ETH_OPEN_MDIX_AUTO if auto MDIX is requested
i. ETH_RES_OK for success
Note: all PHY’s respond to address 0.
supported.
normal/swap mode.