PIC32MX575F256LT-80I/PT Microchip Technology, PIC32MX575F256LT-80I/PT Datasheet - Page 3

• Manufacturer Part Number: PIC32MX575F256LT-80I/PT
• Description: 256KB Flash, 64KB RAM, 80 MHz, USB, 1xCAN, 8 DMA 100 TQFP 12x12x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX575F256LT-80I/PT

• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 2:
© 2010 Microchip Technology Inc.
Note 1:
Regulator
Oscillator
Oscillator
Compare
Module
PORTS
Voltage
Output
UART
UART
UART
UART
JTAG
JTAG
WDT
CAN
CAN
ADC
DMA
USB
USB
SPI
SPI
SPI
SPI
Only those issues indicated in the last column apply to the current silicon revision.
and Two -Speed
Suspend Status
Boundary Scan
UART Receive
Buffer Overrun
INT0 Interrupt
DeviceNet™
Clock Switch
Clock Switch
Frame Mode
Trigger from
Slave Mode
Slave Mode
Error Status
PWM Fault
Input Mode
Conversion
Host Mode
SILICON ISSUE SUMMARY (CONTINUED)
Feature
Start-Up
IrDA
BOR
IrDA
—
—
—
—
—
—
—
®
Number
Item
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
37.
38.
DeviceNet filtering does not function.
A Fault may be erroneously cleared due to an aborted read.
In Slave mode, a TX buffer under-run condition will not assert
the TX interrupt flag.
The TOKBUSY bit does not correctly indicate status when a
transfer completes within the Start of Frame (SOF) threshold.
In Host mode, the interval between the first two SOF packets
may be less than what is specified by the USB specification.
When code-protect is enabled, the WDT is not held in Reset
during the POR RAM Clear Sequence (RCS).
Clock switching and Two-Speed Start-up may cause a
general exception when the reserved bit 8 of the DDPCON
register is ‘0’.
Clock source switching may cause a general exception or
POR when switching from a slow clock to a fast clock.
A wake-up interrupt may not be clearable.
I/O pins do not tri-state immediately, if previously driven high.
Byte writes to the SPISTAT register are not decoded correctly.
Recovery from an underrun requires multiple SPI clock
periods.
The TXBAT bit status may be incorrect after an abort.
The IrDA minimum bit time is not detected at all baud rates.
TX data is corrupted when BRG values greater than 0x200
are used.
On 64-pin devices, the TMS pin requires an external pull-up.
The TRMT bit is asserted before the transmission is
complete.
The OERR bit does not get cleared on a module Reset. The
OERR bit retains its value even after the UART module is
reinitialized.
The ADC module conversion triggers occur on the rising edge
of the INT0 signal even when INT0 is configured to generate
an interrupt on the falling edge.
Pin 100 on 100-pin packages and pin A1 on 121-pin
packages do not respond to boundary scan commands.
The DMABUSY status bit may not reflect the correct status if
the DMA module is suspended.
Device may not exit BOR state if BOR event occurs.
PIC32MX575/675/695/775/795
Issue Summary
DS80480E-page 3
Revisions
Affected
A0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(1)