SSM2380CBZ-REEL Analog Devices Inc, SSM2380CBZ-REEL Datasheet - Page 26

• Manufacturer Part Number: SSM2380CBZ-REEL
• Description: Stereo ClassD Amplifier I2C Gain Control
• Manufacturer: Analog Devices Inc
• Type: Class Dr

Specifications of SSM2380CBZ-REEL

• Output Type: 2-Channel (Stereo)
• Max Output Power X Channels @ Load: 3.2W x 2 @ 4 Ohm
• Voltage - Supply: 2.5 V ~ 5.5 V
• Features: Depop, Differential Inputs, I²C, Mute, Short-Circuit and Thermal Protection
• Mounting Type: Surface Mount
• Package / Case: 16-UFBGA, WLCSP
• Operational Class: Class-D
• Audio Amplifier Output Configuration: 2-Channel Stereo
• Audio Amplifier Function: Speaker
• Single Supply Voltage (typ): 3/5V
• Power Supply Requirement: Single
• Rail/rail I/o Type: No
• Power Supply Rejection Ratio: 85dB
• Single Supply Voltage (min): 2.5V
• Single Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: WLCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SSM2380
REGISTER MAP DETAILS
REGISTER R0: LEFT CHANNEL GAIN CONTROL, ADDRESS 0x00
Bit 7
LTOR
Table 12. Left Channel Gain Control Register Bit Descriptions
Bits
7
6
[5:0]
REGISTER R1: RIGHT CHANNEL GAIN CONTROL, ADDRESS 0x01
Bit 7
RTOL
Table 13. Right Channel Gain Control Register Bit Descriptions
Bits
7
6
[5:0]
Bit Name
LTOR
LMUTE
LGAIN[5:0]
Bit Name
RTOL
RMUTE
RGAIN[5:0]
Bit 6
LMUTE
Bit 6
RMUTE
Description
Left-to-right channel gain data load control.
0 = disable simultaneous loading of left channel gain data to left and right channel registers (default).
1 = enable simultaneous loading of left channel gain data to left and right channel registers.
Left channel input mute.
0 = disable mute (default).
1 = enable mute on left channel amplifier.
Left channel gain control. Each step represents a 0.5 dB increase in gain. For ALC operation, these bits control
the gain setting for both the left and right channels. If the ALC_EN bit in Register R4 is set to 1, these bits cannot
be changed.
Setting
000000
…
100010
…
101101
101110 to 111111
Description
Right-to-left channel gain data load control.
0 = disable simultaneous loading of right channel gain data to left and right channel registers (default).
1 = enable simultaneous loading of right channel gain data to left and right channel registers.
Right channel input mute.
0 = disable mute (default).
1 = enable mute on right channel amplifier.
Right channel gain control. Each step represents a 0.5 dB increase in gain. If the ALC_EN bit in Register R4 is set
to 1, these bits cannot be changed.
Setting
000000
…
100010
…
101101
101110 to 111111
Bit 5
Bit 5
Bit 4
Bit 4
Gain
1 dB
…
18 dB (default)
…
23.5 dB
24 dB
Gain
1 dB
…
18 dB (default)
…
23.5 dB
24 dB
Rev. A | Page 26 of 32
Bit 3
Bit 3
RGAIN[5:0]
LGAIN[5:0]
Bit 2
Bit 2
Bit 1
Bit 1
Bit 0
Bit 0