SSM2517CBZ-R7 Analog Devices Inc, SSM2517CBZ-R7 Datasheet

SSM2517CBZ-R7

Manufacturer Part Number

SSM2517CBZ-R7

Description

Digital PDM-Input Mono 2.5W Classd

Manufacturer

Analog Devices Inc

Type

Class Dr

Datasheet

1.SSM2517CBZ-R7.pdf (16 pages)

Specifications of SSM2517CBZ-R7

Output Type

1-Channel (Mono)

Max Output Power X Channels @ Load

2.4W x 1 @ 4 Ohm

Voltage - Supply

2.5 V ~ 5.5 V

Features

Depop, Digital Inputs, Short-Circuit and Thermal Protection, Shutdown

Mounting Type

Surface Mount

Package / Case

9-WFBGA, CSPBGA

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Other names

SSM2517CBZ-R7TR

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FEATURES

Filterless digital Class-D amplifier

Pulse density modulation (PDM) digital input interface

2.4 W into 4 Ω load and 1.38 W into 8 Ω load at 5.0 V supply

Available in 9-ball, 1.5 mm × 1.5 mm, 0.5 mm pitch WLCSP

92% efficiency into 8 Ω at full scale

Output noise: 43 μV rms at 3.6 V, A-weighted

THD + N: 0.035% at 1 kHz, 100 mW output power

PSRR: 85 dB at 217 Hz, input referred with dither input

Quiescent power consumption: 10.4 mW

Pop-and-click suppression

Configurable with PDM pattern inputs

Short-circuit and thermal protection with autorecovery

Smart power-down when PDM stop condition

64 × f

DC blocking high-pass filter and static input dc protection

User-selectable ultralow EMI emissions mode

Power-on reset (POR)

Minimal external passive components

APPLICATIONS

Mobile handsets

GENERAL DESCRIPTION

The

that offers higher performance than existing DAC plus Class-D

solutions. The SSM2517 is ideal for power sensitive applications,

such as mobile phones and portable media players, where system

noise can corrupt the small analog signal sent to the amplifier.

The SSM2517 combines an audio digital-to-analog converter

(DAC), a power amplifier, and a PDM digital interface on a single

chip. The integrated DAC plus analog Σ-Δ modulator architecture

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

with <1% total harmonic distortion plus noise (THD + N)

(VDD = 1.8 V, PVDD = 3.6 V, 8 Ω + 33 μH load)

or no clock input detected

SSM2517

or 128 × f

is a PDM digital input Class-D power amplifier

operation supporting 3 MHz and 6 MHz clocks

PDAT

PCLK

POWER-ON

INTERFACE

RESET

INPUT

FUNCTIONAL BLOCK DIAGRAM

CLOCKING POWER

FILTERING/

CONTROL

VDD

DAC

Figure 1.

MODULATOR

GAIN_FS

CLASS-D

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

enables extremely low real-world power consumption from

digital audio sources with excellent audio performance. Using

the SSM2517, audio can be transmitted digitally to the audio

amplifier, significantly reducing the effect of noise sources such as

GSM interference or other digital signals on the transmitted audio.

The SSM2517 is capable of delivering 2.4 W of continuous output

power with <1% THD + N driving a 4 Ω load from a 5.0 V supply.

The SSM2517 features a high efficiency, low noise modulation

scheme that requires no external LC output filters. The closed-loop,

three-level modulator design retains the benefits of an all-digital

amplifier, yet enables very good PSRR and audio performance. The

modulation continues to provide high efficiency even at low output

power and has an SNR of 96 dB. Spread-spectrum pulse density

modulation is used to provide lower EMI-radiated emissions

compared with other Class-D architectures.

The SSM2517 has a four-state gain and sample frequency selection

pin that can select two different gain settings, optimized for 3.6 V

and 5 V operation. This same pin also controls the internal digital

filtering and clocking, which can be set for 64 × f

sample rates to support both 3 MHz and 6 MHz PDM clock rates.

The SSM2517 has a micropower shutdown mode with a typical

shutdown current of 1 μA for both power supplies. Shutdown is

enabled automatically by gating input clock and data signals. A

standby mode can be entered by applying a designated PDM stop

condition sequence. The device also includes pop-and-click sup-

pression circuitry. This suppression circuitry minimizes voltage

glitches at the output when entering or leaving the low power

state, reducing audible noises on activation and deactivation.

The SSM2517 is specified over the industrial temperature range

of −40°C to +85°C. It has built-in thermal shutdown and output

short-circuit protection. It is available in a 9-ball, 1.5 mm × 1.5 mm

wafer level chip scale package (WLCSP).

Σ-Δ

2.4 W Class-D Audio Amplifier

PDM Digital Input, Mono

POWER STAGE

PVDD

FULL-BRIDGE

SSM2517

LRSEL

PGND

OUT+

OUT–

SSM2517

or 128 × f

www.analog.com

input

Related parts for SSM2517CBZ-R7

SSM2517CBZ-R7 Summary of contents

Page 1

FEATURES Filterless digital Class-D amplifier Pulse density modulation (PDM) digital input interface 2.4 W into 4 Ω load and 1.38 W into 8 Ω load at 5.0 V supply with <1% total harmonic distortion plus noise (THD + N) Available ...

Page 2

SSM2517 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Digital Input Specifications ......................................................... 4 PDM Interface Digital Timing Specifications .......................... 5 Absolute Maximum ...

Page 3

SPECIFICATIONS PVDD = 5.0 V, VDD = 1 128× when f = 64×, PDM clock = 3.072 MHz. S Table 1. Parameter DEVICE CHARACTERISTICS Output Power Total Harmonic Distortion Plus Noise Efficiency Average Switching Frequency ...

Page 4

SSM2517 Parameter Standby Current Shutdown Current NOISE PERFORMANCE Output Voltage Noise Signal-to-Noise Ratio DIGITAL INPUT SPECIFICATIONS Table 2. Parameter INPUT SPECIFICATIONS Input Voltage High PCLK, PDAT, LRSEL Pins GAIN_FS Pin Input Voltage Low PCLK, PDAT, LRSEL Pins GAIN_FS Pin Input ...

Page 5

PDM INTERFACE DIGITAL TIMING SPECIFICATIONS Table 3. Limit Parameter t MIN The SSM2517 was designed so that the data line can transition coincident with or close to a clock edge. ...

Page 6

SSM2517 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings apply at 25°C, unless otherwise noted. Table 4. Parameter PVDD Supply Voltage VDD Supply Voltage Input Voltage (Signal Source) ESD Susceptibility OUT− and OUT+ Pins Storage Temperature Range Operating Temperature Range Junction Temperature ...

Page 7

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 6. Pin Function Descriptions Pin No. Mnemonic Function A1 OUT+ Output A2 PVDD Supply A3 PGND Ground B1 OUT− Output B2 LRSEL Input B3 VDD Supply C1 PCLK Input C2 PDAT Input C3 GAIN_FS ...

Page 8

SSM2517 TYPICAL PERFORMANCE CHARACTERISTICS 100 R = 8Ω + 33µH L GAIN = 5V SAMPLE RATE = 64× (3.072MHz PVDD = 2.5V 0.1 0.01 0.001 0.01 0.1 OUTPUT POWER (W) Figure 4. THD + N vs. Output Power ...

Page 9

R = 4Ω + 15µH L GAIN = 3.6V SAMPLE RATE = 64× (3.072MHz) 10 PVDD = 3.6V 1 PVDD = 2.5V 0.1 0.01 0.001 0.01 0.1 OUTPUT POWER (W) Figure 10. THD + N vs. Output Power into ...

Page 10

SSM2517 100 R = 8Ω + 33µH L PVDD = 2.5V GAIN = 3.6V SAMPLE RATE = 64× 10 (3.072MHz) 1 0.2W 0.1W 0.1 0.05W 0.01 10 100 1k FREQUENCY (Hz) Figure 16. THD + N vs. Frequency, PVDD = ...

Page 11

R = 4Ω + 15µH L GAIN = 5V 3.0 SAMPLE RATE = 64× (3.072MHz) 2.5 2.0 THD + N = 10% 1.5 THD + 1.0 0.5 0 3.0 3.5 4.0 2.5 SUPPLY VOLTAGE (V) Figure ...

Page 12

SSM2517 0 –10 –20 –30 –40 –50 –60 PVDD = 3.6V –70 –80 PVDD = 5V –90 –100 10 100 1k FREQUENCY (Hz) Figure 28. Power Supply Rejection Ratio (PSRR) vs. Frequency –1 –2 ...

Page 13

THEORY OF OPERATION MASTER CLOCK The SSM2517 requires a clock present at the PCLK input pin. This clock must be fully synchronous with the incoming digital audio on the serial interface. The clock frequencies must fall into one of these ...

Page 14

SSM2517 PDM PATTERN CONTROL The SSM2517 has a simple control mechanism that can set the part for low power states and control functionality. This is accomplished by sending a repeating 8-bit pattern to the device. Different patterns set different functionality ...

Page 15

APPLICATIONS INFORMATION LAYOUT As output power increases, care must be taken to lay out PCB traces and wires properly among the amplifier, load, and power supply. A good practice is to use short, wide PCB tracks to decrease voltage drops ...

Page 16

... BALL A1 IDENTIFIER TOP VIEW (BALL SIDE DOWN) ORDERING GUIDE 1 Model Temperature Range SSM2517CBZ-R7 −40°C to +85°C SSM2517CBZ-RL −40°C to +85°C EVAL-SSM2517Z RoHS Compliant Part. ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...

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