SST25VF040B-80-4I-S2AE-T Microchip Technology, SST25VF040B-80-4I-S2AE-T Datasheet - Page 17

• Manufacturer Part Number: SST25VF040B-80-4I-S2AE-T
• Description: 2.7V To 3.6V 4Mbit SPI Serial Flash 8 SOIJ .208in T/R
• Manufacturer: Microchip Technology

Specifications of SST25VF040B-80-4I-S2AE-T

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 80MHz
• Interface: SPI Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (0.200", 5.30mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4 Mbit SPI Serial Flash
SST25VF040B
Chip-Erase
The Chip-Erase instruction clears all bits in the device to
FFH. A Chip-Erase instruction will be ignored if any of the
memory area is protected. Prior to any Write operation, the
Write-Enable (WREN) instruction must be executed. CE#
must remain active low for the duration of the Chip-Erase
instruction sequence. The Chip-Erase instruction is initiated
Read-Status-Register (RDSR)
The Read-Status-Register (RDSR) instruction allows read-
ing of the status register. The status register may be read at
any time even during a Write (Program/Erase) operation.
When a Write operation is in progress, the Busy bit may be
checked before sending any new commands to assure that
the new commands are properly received by the device.
Write-Enable (WREN)
The Write-Enable (WREN) instruction sets the Write-
Enable-Latch bit in the Status Register to 1 allowing Write
operations to occur. The WREN instruction must be exe-
cuted prior to any Write (Program/Erase) operation. The
WREN instruction may also be used to allow execution of
the Write-Status-Register (WRSR) instruction; however,
the Write-Enable-Latch bit in the Status Register will be
©2009 Silicon Storage Technology, Inc.
FIGURE 15: Chip-Erase Sequence
FIGURE 16: Read-Status-Register (RDSR) Sequence
SCK
CE#
SO
SI
MODE 3
MODE 0
MSB
0
1
HIGH IMPEDANCE
2
SCK
CE#
SO
SI
3
05
MODE 3
MODE 0
4
5
HIGH IMPEDANCE
MSB
0 1 2 3 4 5 6 7
6
17
60 or C7
7
by executing an 8-bit command, 60H or C7H. CE# must be
driven high before the instruction is executed. The user may
poll the Busy bit in the software status register or wait T
for the completion of the internal self-timed Chip-Erase
cycle. See Figure 15 for the Chip-Erase sequence.
CE# must be driven low before the RDSR instruction is
entered and remain low until the status data is read. Read-
Status-Register is continuous with ongoing clock cycles
until it is terminated by a low to high transition of the CE#.
See Figure 16 for the RDSR instruction sequence.
cleared upon the rising edge CE# of the WRSR instruction.
CE# must be driven high before the WREN instruction is
executed.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
8
1295 ChEr.0
9
10
Register Out
11
Status
12
13
14
1295 RDSRseq.0
S71295-05-000
Data Sheet
10/09
CE