SST39VF1602-70-4C-EKE-T Microchip Technology, SST39VF1602-70-4C-EKE-T Datasheet - Page 3

• Manufacturer Part Number: SST39VF1602-70-4C-EKE-T
• Description: 2.7V To 3.6V 16Mbit Multi-Purpose Flash 48 TSOP 12x20 Mm T/R
• Manufacturer: Microchip Technology

Specifications of SST39VF1602-70-4C-EKE-T

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 16M (1M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-TFSOP (0.472", 12.0mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
To resume Sector-Erase or Block-Erase operation which has
been suspended the system must issue Erase Resume
command. The operation is executed by issuing one byte
command sequence with Erase Resume command (30H)
at any address in the last Byte sequence.
Chip-Erase Operation
The SST39VF160x/320x provide a Chip-Erase operation,
which allows the user to erase the entire memory array to
the “1” state. This is useful when the entire device must be
quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command
(10H) at address 5555H in the last byte sequence. The
Erase operation begins with the rising edge of the sixth
WE# or CE#, whichever occurs first. During the Erase
operation, the only valid read is Toggle Bit or Data# Polling.
See Table 6 for the command sequence, Figure 10 for tim-
ing diagram, and Figure 24 for the flowchart. Any com-
mands issued during the Chip-Erase operation are
ignored. When WP# is low, any attempt to Chip-Erase will
be ignored. During the command sequence, WP# should
be statically held high or low.
Write Operation Status Detection
The SST39VF160x/320x provide two software means to
detect the completion of a Write (Program or Erase) cycle,
in order to optimize the system write cycle time. The soft-
ware detection includes two status bits: Data# Polling
(DQ
mode is enabled after the rising edge of WE#, which ini-
tiates the internal Program or Erase operation.
The actual completion of the nonvolatile write is asyn-
chronous with the system; therefore, either a Data# Poll-
ing or Toggle Bit read may be simultaneous with the
completion of the write cycle. If this occurs, the system
may possibly get an erroneous result, i.e., valid data may
appear to conflict with either DQ
vent spurious rejection, if an erroneous result occurs, the
software routine should include a loop to read the
accessed location an additional two (2) times. If both
reads are valid, then the device has completed the Write
cycle, otherwise the rejection is valid.
Data# Polling (DQ
When the SST39VF160x/320x are in the internal Program
operation, any attempt to read DQ
plement of the true data. Once the Program operation is
completed, DQ
though DQ
©2008 Silicon Storage Technology, Inc.
7
) and Toggle Bit (DQ
7
may have valid data immediately following the
7
will produce true data. Note that even
7
)
6
). The End-of-Write detection
7
or DQ
7
will produce the com-
6
. In order to pre-
3
completion of an internal Write operation, the remaining
data outputs may still be invalid: valid data on the entire
data bus will appear in subsequent successive Read
cycles after an interval of 1 µs. During internal Erase oper-
ation, any attempt to read DQ
internal Erase operation is completed, DQ
‘1’. The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block- or Chip-Erase, the Data# Polling is valid after the
rising edge of sixth WE# (or CE#) pulse. See Figure 7 for
Data# Polling timing diagram and Figure 21 for a flowchart.
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
and “0”s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ
stop toggling. The device is then ready for the next opera-
tion. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ
is valid after the rising edge of sixth WE# (or CE#) pulse.
DQ
Erase-Suspended Sector/Block. If Program operation is ini-
tiated in a sector/block not selected in Erase-Suspend
mode, DQ
An additional Toggle Bit is available on DQ
used in conjunction with DQ
sector is being actively erased or erase-suspended. Table 1
shows detailed status bits information. The Toggle Bit
(DQ
pulse of Write operation. See Figure 8 for Toggle Bit timing
diagram and Figure 21 for a flowchart.
TABLE 1: Write Operation Status
Note: DQ
Status
Normal
Operation
Erase-
Suspend
Mode
6
2
will be set to “1” if a Read operation is attempted on an
) is valid after the rising edge of the last WE# (or CE#)
status information.
7
and DQ
6
Standard
Program
Standard
Erase
Read from
Erase-Suspended
Sector/Block
Read from
Non- Erase-Suspended
Sector/Block
Program
will toggle.
2
require a valid address when reading
6
6
to check whether a particular
7
will produce alternating “1”s
will produce a ‘0’. Once the
DQ
DQ
DQ
Data
0
1
7
7
7
#
#
S71223-05-000
Toggle
Toggle
Toggle
DQ
Data
7
2
1
, which can be
will produce a
6
Data Sheet
No Toggle
Toggle
Toggle
6
DQ
Data
T1.0 1223
N/A
bit will
2
6/08
6
)