STK22C48-NF45 Cypress Semiconductor Corp, STK22C48-NF45 Datasheet - Page 4

• Manufacturer Part Number: STK22C48-NF45
• Description: STK22C48-NF45
• Manufacturer: Cypress Semiconductor Corp
• Type: NVSRAMr

Specifications of STK22C48-NF45

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 16K (2K x 8)
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Word Size: 8b
• Organization: 2Kx8
• Density: 16Kb
• Interface Type: Parallel
• Access Time (max): 45ns
• Operating Supply Voltage (typ): 5V
• Package Type: SOIC
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: 0C to 70C
• Pin Count: 28
• Mounting: Surface Mount
• Supply Current: 65mA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Device Operation
The STK22C48 nvSRAM is made up of two functional
components paired in the same physical cell. These are an
SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables the storage and
recall of all cells in parallel. During the STORE and RECALL
operations, SRAM Read and Write operations are inhibited. The
STK22C48 supports unlimited reads and writes similar to a
typical SRAM. In addition, it provides unlimited RECALL
operations from the nonvolatile cells and up to one million
STORE operations.
SRAM Read
The STK22C48 performs a Read cycle whenever CE and OE are
LOW while WE and HSB are HIGH. The address specified on
pins A
Read is initiated by an address transition, the outputs are valid
after a delay of t
or OE, the outputs are valid at t
(Read cycle 2). The data outputs repeatedly respond to address
changes within the t
transitions on any control input pins, and remains valid until
another address change or until CE or OE is brought HIGH, or
WE or HSB is brought LOW.
SRAM Write
A Write cycle is performed whenever CE and WE are LOW and
HSB is HIGH. The address inputs must be stable prior to entering
the Write cycle and must remain stable until either CE or WE
goes HIGH at the end of the cycle. The data on the common I/O
pins DQ
the end of a WE controlled Write or before the end of an CE
controlled Write. Keep OE HIGH during the entire Write cycle to
avoid data bus contention on common I/O lines. If OE is left LOW,
internal circuitry turns off the output buffers t
LOW.
AutoStore Operation
During normal operation, the device draws current from V
charge a capacitor connected to the V
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
automatically disconnects the V
operation is initiated with power provided by the V
Figure 2
(V
between 68 µF and 220 µF (+20%) rated at 6 V should be
Document Number: 001-51000 Rev. *D
CAP
) for automatic store operation. A charge storage capacitor
0–10
0–7
shows the proper connection of the storage capacitor
determines the 2,048 data bytes accessed. When the
are written into the memory if it has valid t
AA
(Read cycle 1). If the Read is initiated by CE
AA
CC
access time without the need for
pin drops below V
ACE
CAP
or at t
pin from V
DOE
CAP
HZWE
, whichever is later
SWITCH
pin. This stored
CC
after WE goes
CAP
. A STORE
SD
, the part
capacitor.
, before
CC
to
In system power mode, both V
+5 V power supply without the 68 μF capacitor. In this mode, the
AutoStore function of the STK22C48 operates on the stored
system charge as power goes down. The user must, however,
guarantee that V
STORE cycle.
To prevent unneeded STORE operations, automatic STOREs
and those initiated by externally driving HSB LOW are ignored,
unless at least one
recent STORE or RECALL cycle. An optional pull-up resistor is
shown connected to HSB. This is used to signal the system that
the AutoStore cycle is in progress.
AutoStore Inhibit mode
If an automatic STORE on power loss is not required, then V
is tied to ground and +5 V is applied to V
5). This is the AutoStore Inhibit mode, where the AutoStore
function is disabled. If the STK22C48 is operated in this config-
uration, references to V
data sheet. In this mode, STORE operations are triggered with
the HSB pin. It is not permissible to change between these three
options “on the fly”.
Figure 2. AutoStore Mode
CC
WRITE
does not drop below 3.6 V during the 10 ms
CC
operation takes place since the most
are changed to V
CC
and V
CAP
CAP
are connected to the
CAP
STK22C48
(Figure 3 on page
throughout this
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