STM8AF6268TDX STMicroelectronics, STM8AF6268TDX Datasheet - Page 21

• Manufacturer Part Number: STM8AF6268TDX
• Description: 8 BITS MICROCONTR
• Manufacturer: STMicroelectronics
• Series: STM8Ar

Specifications of STM8AF6268TDX

• Core Processor: STM8A
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 32-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

STM8AF61xx, STM8AF62xx
5.9.1
5.9.2
Serial peripheral interface (SPI)
The devices covered by this datasheet contain one SPI. The SPI is available on all the
supported packages.
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Inter integrated circuit (I
The devices covered by this datasheet contain one I
on all the supported packages.
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Maximum speed: 10 Mbit/s or f
Full duplex synchronous transfers
Simplex synchronous transfers on two lines with a possible bidirectional data line
Master or slave operation - selectable by hardware or software
CRC calculation
1 byte Tx and Rx buffer
Slave mode/master mode management by hardware or software for both master and
slave
Programmable clock polarity and phase
Programmable data order with MSB-first or LSB-first shifting
Dedicated transmission and reception flags with interrupt capability
SPI bus busy status flag
Hardware CRC feature for reliable communication:
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I
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I
–
–
Generation and detection of 7-bit/10-bit addressing and general call
Supports different communication speeds:
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Status flags:
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Error flags:
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Interrupt:
2
2
C master features:
C slave features:
CRC value can be transmitted as last byte in Tx mode
CRC error checking for last received byte
Clock generation
Start and stop generation
Programmable I
Stop bit detection
Standard speed (up to 100 kHz),
Fast speed (up to 400 kHz)
Transmitter/receiver mode flag
End-of-byte transmission flag
I
Arbitration lost condition for master mode
Acknowledgement failure after address/data transmission
Detection of misplaced start or stop condition
Overrun/underrun if clock stretching is disabled
2
C busy flag
2
C address detection
Doc ID 14952 Rev 5
2
C) interface
MASTER
/2 both for master and slave
2
C interface. The interface is available
Product overview
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