STM8AF6269TCY STMicroelectronics, STM8AF6269TCY Datasheet - Page 23

• Manufacturer Part Number: STM8AF6269TCY
• Description: 8 BITS MICROCONTR
• Manufacturer: STMicroelectronics
• Series: STM8Ar

Specifications of STM8AF6269TCY

• Core Processor: STM8A
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

STM8AF52/62xx, STM8AF51/61xx
5.9.2
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Universal asynchronous receiver/transmitter with LIN support
(LINUART)
The devices covered by this datasheet contain one LINUART interface. The interface is
available on all the supported packages. The LINUART is an asynchronous serial
High-precision baud rate generator system
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Programmable data word length (8 or 9 bits)
Configurable stop bits: Support for 1 or 2 stop bits
LIN master mode:
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Transmitter clock output for synchronous communication
Separate enable bits for transmitter and receiver
Transfer detection flags:
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Parity control:
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Four error detection flags:
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Six interrupt sources with flags:
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Two interrupt vectors:
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Reduced power consumption mode
Wakeup from mute mode (by idle line detection or address mark detection)
Two receiver wakeup modes:
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Common programmable transmit and receive baud rates up to f
LIN break and delimiter generation
LIN break and delimiter detection with separate flag and interrupt source for
readback checking.
Receive buffer full
Transmit buffer empty
End of transmission flags
Transmits parity bit
Checks parity of received data byte
Overrun error
Noise error
Frame error
Parity error
Transmit data register empty
Transmission complete
Receive data register full
Idle line received
Parity error
LIN break and delimiter detection
Transmitter interrupt
Receiver interrupt
Address bit (MSB)
Idle line
Doc ID 14395 Rev 8
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