STM8L152M8T6 STMicroelectronics, STM8L152M8T6 Datasheet - Page 59

• Manufacturer Part Number: STM8L152M8T6
• Description: 8 BITS MICROCONTR
• Manufacturer: STMicroelectronics
• Series: STM8L EnergyLiter

Specifications of STM8L152M8T6

• Core Processor: STM8
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, IR, LCD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 28x12b, D/A 2x12
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

STM8L15xx8, STM8L15xR6
Table 11.
1. The Low power wait mode is entered when executing a WFE instruction in Low power run mode.
2. The TLI interrupt is the logic OR between TIM2 overflow interrupt, and TIM4 overflow interrupts.
3. In WFE mode, this interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes
4. The interrupt from PVD is logically OR-ed with Port E and F interrupts. Register EXTI_CONF allows to select between Port
5. The device is woken up from Halt or Active-halt mode only when the address received matches the interface address.
IRQ
No.
20
21
22
23
24
25
26
27
28
29
back to WFE mode. When this interrupt is configured as a wakeup event, the CPU wakes up and resumes processing.
E and Port F interrupt (see
USART 1/
USART 1/
I
USART2
USART3
USART3
2
Source
C1/SPI2
block
TIM2/
TIM3/
TIM3/
TIM1
TIM1
TIM4
TIM5
TIM5
SPI1
Interrupt mapping (continued)
Capture/Compare/USART
2 interrupt
TIM3 Update
/Overflow/Trigger/Break/
USART3 transmission
complete/transmit data
register empty
interrupt
TIM3 Capture/Compare/
USART3 Receive register
data full/overrun/idle line
detected/parity error/
interrupt
Update /overflow/trigger/
COM
Capture/Compare
Update/overflow/trigger
End of Transfer
USART1 transmission
complete/transmit data
register empty/
TIM5 update/overflow/
trigger/break
USART1 Receive register
data full/overrun/idle line
detected/parity error/
TIM5 capture/compare
I
SPI2
2
C1 interrupt
Description
External interrupt port select register (EXTI_CONF)
(5)
/
Doc ID 17943 Rev 4
from Halt
Wakeup
mode
Yes
Yes
-
-
-
-
-
-
-
-
Active-halt
Wakeup
mode
from
Yes
Yes
-
-
-
-
-
-
-
-
in the RM0031).
from Wait
Wakeup
mode)
(WFI
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
-
Interrupt vector mapping
from Wait
mode)
Wakeup
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
(WFE
Yes
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(1)
0x00 805C
0x00 806C
0x00 807C
0x00 8058
0x00 8060
0x00 8064
0x00 8068
0x00 8070
0x00 8074
0x00 8078
address
Vector
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