SX1233IMLTRT Semtech, SX1233IMLTRT Datasheet
SX1233IMLTRT
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Page 1
... Automatic RF Sense with ultra-fast AFC Packet engine with CRC, AES-128 encryption and 66- byte FIFO Built-in temperature sensor and Low Battery indicator ORDERING INFORMATION Part Number SX1233IMLTRT QFN 24 Package - Operating Range [-40;+85°C] Pb-free, Halogen free, RoHS/WEEE compliant product Page 1 RESET SPI ...
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... Automatic Gain Control................................................................................................................................................. 24 3.5.4. Continuous-Time DAGC ............................................................................................................................................... 25 3.5.5. Quadrature Mixer - ADCs - Decimators........................................................................................................................ 26 3.5.6. Channel Filter ............................................................................................................................................................... 26 3.5.7. DC Cancellation............................................................................................................................................................ 27 3.5.8. Complex Filter - OOK ................................................................................................................................................... 27 3.5.9. RSSI ............................................................................................................................................................................. 27 3.5.10. Cordic ......................................................................................................................................................................... 28 3.5.11. FSK Demodulator ....................................................................................................................................................... 29 3.5.12. OOK Demodulator ...................................................................................................................................................... 29 3.5.13. Bit Synchronizer.......................................................................................................................................................... 31 Rev 5 - June 2011 Page 2 SX1233 DATASHEET Page www.semtech.com ...
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... DIO Pins Mapping in Packet Mode............................................................................................................................... 49 5.4. Continuous Mode.............................................................................................................................................................. 50 5.4.1. General Description ...................................................................................................................................................... 50 5.4.2. Tx Processing ............................................................................................................................................................... 50 5.4.3. Rx Processing............................................................................................................................................................... 51 5.5. Packet Mode..................................................................................................................................................................... 51 5.5.1. General Description ...................................................................................................................................................... 51 5.5.2. Packet Format .............................................................................................................................................................. 52 5.5.3. Tx Processing (without AES) ........................................................................................................................................ 54 5.5.4. Rx Processing (without AES)........................................................................................................................................ 55 Rev 5 - June 2011 Page 3 SX1233 DATASHEET Page www.semtech.com ...
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... Figure 10. Cordic Extraction .............................................................................................................................................................. 28 Figure 11. OOK Peak Demodulator Description ............................................................................................................................... 29 Figure 12. Floor Threshold Optimization ........................................................................................................................................... 30 Figure 13. Bit Synchronizer Description ............................................................................................................................................ 31 Figure 14. FEI Process ..................................................................................................................................................................... 32 Figure 15. Optimized AFC (AfcLowBetaOn=1) ................................................................................................................................. 33 Figure 16. Temperature Sensor Response ....................................................................................................................................... 34 Figure 17. Tx Startup, FSK and OOK ............................................................................................................................................... 37 Rev 5 - June 2011 Page 4 SX1233 DATASHEET Page www.semtech.com ...
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... Table 8. Digital Specification .............................................................................................................................................................. 15 Table 9. Bit Rate Examples ................................................................................................................................................................ 20 Table 10. Power Amplifier Mode Selection Truth Table ..................................................................................................................... 21 Table 11. LNA Gain Settings .............................................................................................................................................................. 23 Table 12. Receiver Performance Summary ....................................................................................................................................... 25 Table 13. Available RxBw Settings .................................................................................................................................................... 26 Table 14. Available DCC Cutoff Frequencies .................................................................................................................................... 27 Table 15. Basic Transceiver Modes ................................................................................................................................................... 36 Rev 5 - June 2011 Page 5 SX1233 DATASHEET Page www.semtech.com ...
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... Table 25. Receiver Registers ............................................................................................................................................................. 68 Table 26. IRQ and Pin Mapping Registers ......................................................................................................................................... 70 Table 27. Packet Engine Registers .................................................................................................................................................... 72 Table 28. Temperature Sensor Registers .......................................................................................................................................... 75 Table 29. Test Registers .................................................................................................................................................................... 75 Table 30. Crystal Specification ........................................................................................................................................................... 76 Table 31. +13dBm BOM .................................................................................................................................................................... 78 Table 32. +17dBm BOM .................................................................................................................................................................... 78 Table 33. Chip Identification ............................................................................................................................................................... 82 Table 34. Revision History ................................................................................................................................................................. 83 Rev 5 - June 2011 Page 6 SX1233 DATASHEET Page www.semtech.com ...
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... Phase-Locked Loop POR Power On Reset RBW Resolution BandWidth RF Radio Frequency RSSI Received Signal Strength Indicator Rx Receiver SAW Surface Acoustic Wave SPI Serial Peripheral Interface SR Shift Register Stby Standby Tx Transmitter uC Microcontroller VCO Voltage Controlled Oscillator XO Crystal Oscillator XOR eXclusive OR Page 7 SX1233 DATASHEET www.semtech.com ...
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... ADVANCED COMMUNICATIONS & SENSING This product datasheet contains a detailed description of the SX1233 performance and functionality. Please consult the Semtech website for the latest updates or errata. Refer to section 9 of this document to identify chip revisions. 1. General Description The SX1233 is a single-chip integrated circuit ideally suited for today's high performance ISM band RF applications. The SX1233's advanced features set, including state of the art packet engine greatly simplifies system design whilst the high level of integration reduces the external BOM to a handful of passive decoupling and matching components ...
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... Pin and Marking Diagram The following diagram shows the pin arrangement of the QFN package, top view. Notes yyww refers to the date code xxxxxx refers to the lot number Rev 5 - June 2011 Figure 2. Pin Diagram SX12BC Figure 3. Marking Diagram Page 9 SX1233 DATASHEET www.semtech.com ...
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... SPI Clock input O MISO SPI Data output I MOSI SPI Data input I NSS SPI Chip select input O RXTX Rx/Tx switch control: high GND Ground I/O RFIO RF input / output - GND Ground O Optional high-power PA output - VR_PA Regulated supply for the PA Page 10 SX1233 DATASHEET Description www.semtech.com ...
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... Supply voltage Top Operational temperature range Clop Load capacitance on digital ports ML RF Input Level Rev 5 - June 2011 Description Description Page 11 SX1233 DATASHEET Min Max Unit -0.5 3.9 V -55 +115 ° +125 ° dBm Min Max Unit 1.8 3.6 V -40 +85 ° dBm www.semtech.com ...
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... MHz step 5 MHz step 7 MHz step 12 MHz step 20 MHz step 25 MHz step Page 12 SX1233 DATASHEET Min Typ Max Unit - 0 1 1.25 1 Min Typ Max Unit 290 - 340 MHz 431 - 510 MHz 862 - 1020 MHz - 32 - MHz - 250 500 150 www.semtech.com ...
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... Offset = +/- 10 MHz Lowest LNA gain Highest LNA gain Page 13 SX1233 DATASHEET - 61 62.5 - kHz 1.2 - 600 kbps 1.2 - 32.768 kbps 0.6 - 300 kHz Min Typ Max Unit - -118 - dBm - -105 - dBm - - 97 - dBm - - 92 - dBm - -120 - dBm - -112 -109 dBm -13 - +75 - dBm - +35 - dBm www.semtech.com ...
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... EN 300 220-1 V2.1.1 Frequency Synthesizer enabled, PaRamp = 10 us 4.8 kb/s. Page 14 SX1233 DATASHEET - +20 - dBm -23 -18 - dBm 2.6 - 500 kHz 1 3.0 ms 163 us 4.8 ms 265 bit - 4 bit - 2 bit - -115 - dBm - 0 - dBm Min Typ Max Unit - +13 - dBm - -18 - dBm - +17 - dBm - +/-0 -95 - dBc -37 dBm - 120 - us www.semtech.com ...
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... MOSI change to SCK rising edge from SCK rising edge to MOSI change from NSS falling edge to SCK rising edge from SCK falling edge to NSS rising edge, normal mode Page 15 SX1233 DATASHEET Min Typ Max Unit 0 VDD - - 0.2 VDD 0 VDD - - 0.1 VDD - - 10 MHz 250 - - ns www.semtech.com ...
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... XTA (pin 4). XTB (pin 5) should be left open. The peak-peak amplitude of the input signal must never exceed 1.8 V. Please consult your TCXO supplier for an appropriate value of decoupling capacitor, C Rev 5 - June 2011 . D XTA XTB NC TCXO OP 32 MHz Vcc Vcc GND C D Figure 4. TCXO Connection Page 16 SX1233 DATASHEET www.semtech.com ...
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... The Frf setting is split across 3 bytes. A change in the center frequency will only be taken into account when the least significant byte FrfLsb in RegFrfLsb is written. This allows for more complex modulation schemes such as m- ary FSK, where frequency modulation is achieved by changing the programmed RF frequency. Rev 5 - June 2011 F XOSC --------------- - = F STEP 19 2 × = Frf STEP Page 17 SX1233 DATASHEET www.semtech.com ...
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... Please refer to Table 20 and Table 21 to map this interrupt to the desired pins. Note The lock detect block may indicate an unlock condition (signal toggling low) when the transmitter is FSK modulated with large frequency deviation settings. Rev 5 - June 2011 5 ------------------- - = T PLLAFC PLLBW Page 18 SX1233 DATASHEET www.semtech.com ...
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... In Packet mode or in Continuous mode with Gaussian filtering enabled (refer to section 5.5 for details), the Bit Rate (BR) is controlled by bits BitRate in RegBitrate: Amongst others, the following Bit Rates are accessible: Rev 5 - June 2011 LNA RFIO PA0 PA1 PA_BOOST PA2 Figure 5. Transmitter Block Diagram F XOSC ------------------- - = BR BitRate Page 19 DATASHEET Receiver Chain Local Oscillator SX1233 www.semtech.com ...
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... DATASHEET Actual BR OOK (b/s) 1.2 kbps 1200.015 2.4 kbps 2400.060 4.8 kbps 4799.760 9.6 kbps 9600.960 19.2 kbps 19196.16 38415.36 76738.60 153846.1 57553.95 115107.9 12.5 kbps 12500.00 25 kbps 25000.00 50000.00 100000.0 150234.7 200000.0 250000.0 299065.4 500000.0 603774.0 32.768 kbps 32753.32 www.semtech.com ...
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... PA1 enabled on pin PA_BOOST PA1 and PA2 combined on pin PA_BOOST 1 1 Rev 5 - June 2011 Mode Power Range -18 to +13 dBm -18 to +13 dBm +2 to +17 dBm Other combinations Reserved Page 21 SX1233 DATASHEET Pout OutputPower Formula Range -18 dBm + OutputPower -18 dBm + OutputPower -14 dBm + OutputPower www.semtech.com ...
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... Imax sets the maximum current drawn by the final PA stage, and does not account for the PA drivers and frequency synthesizer. Global current drain on Vbat will be higher. Rev 5 - June 2011 Pout vs. Programmed Power -14 - Program m ed Pow er [dBm ] Figure 6. Output Power Curves × OcpTrim Imax mA Page 22 SX1233 DATASHEET Pout on PA0 [dBm] Pout on PA1 [dBm] Pout on PA1+PA2 [dBm www.semtech.com ...
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... Max gain - 6 dB 011 Max gain - 12 dB 100 Max gain - 24 dB 101 Max gain - 36 dB 110 Max gain - 48 dB 111 Reserved Page 23 SX1233 DATASHEET CORDIC Complex Filter Phase FSK Output Demodulator Module RSSI Output Demodulator Bypassed in FSK Gain Setting - www.semtech.com OOK ...
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... Lower Linearity Lower Noise Figure The following table summarizes the performance (typical figures) of the complete receiver: Rev 5 - June 2011 7dB 11dB G2 G3 Figure 8. AGC Thresholds Settings Page 24 SX1233 DATASHEET Pin [dBm] 9dB 11dB Lower Sensitivity Higher Linearity Higher Noise Figure www.semtech.com ...
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... See section 9.1 for details recommended to always enable the DAGC. Rev 5 - June 2011 Gain Receiver Performance (typ) Setting P NF -1dB [dB] [dBm] [dBm >- >0 44 Page 25 SX1233 DATASHEET IIP3 IIP2 [dBm] -18 +35 -15 +40 -8 +48 -1 +62 +13 +68 +20 +75 www.semtech.com ...
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... RxBwExp × 2 RxBwMant FXOSC ----------------------------------------------------------------- - = RxBw + 3 RxBwExp × 2 RxBwMant RxBwExp RxBw (kHz) (decimal) FSK ModulationType=00 7 2.6 7 3.1 7 3.9 6 5.2 6 6.3 6 7.8 5 10.4 5 12.5 5 15.6 4 20.8 Page 26 SX1233 DATASHEET OOK ModulationType=01 1.3 1.6 2.0 2.6 3.1 3.9 5.2 6.3 7.8 10.4 www.semtech.com ...
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... RxBw). The Local Oscillator is automatically offset by the IF in the OOK receiver. Page 27 DATASHEET 12.5 15.6 20.8 25.0 31.3 41.7 50.0 62.5 83.3 100.0 125.0 166.7 200.0 250 0.5 0.25 0.125 www.semtech.com SX1233 ...
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... Amplitude output: used by the RSSI block, for FSK demodulation, AGC and automatic gain calibration purposes. Rev 5 - June 2011 RSSI Chart - With AGC -120 -110 -100 -90 -80 -70 -60 -50 Pin [dBm] Figure 9. RSSI Dynamic Curve Q(t) Real-time Magnitude Real-time Phase Figure 10. Cordic Extraction Page 28 SX1233 DATASHEET -40 -30 -20 -10 0 I(t) www.semtech.com ...
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... BR Zoom Zoom Decay defined in OokPeakThreshStep Period as defined in OokPeakThreshDec Figure 11. OOK Peak Demodulator Description Page 29 10 ‘’Peak -6dB’’ Threshold ‘’Floor’’ threshold defined by OokFixedThresh Noise floor of receiver Fixed 6dB difference SX1233 DATASHEET Time www.semtech.com ...
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... Average Threshold: Data supplied by the RSSI block is averaged, and this operation mode should only be used with DC-free encoded data. Rev 5 - June 2011 Set SX1233 in OOK Rx mode Adjust Bit Rate, Channel filter BW Default OokFixedThresh setting No input signal Continuous Mode Monitor DIO2/DATA pin Increment OokFixedThresh Glitch activity on DATA ? Optimization complete Figure 12. Floor Threshold Optimization Page 30 SX1233 DATASHEET www.semtech.com ...
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... This function provides information about the frequency error of the local oscillator (LO) compared with the carrier frequency of a modulated signal at the input of the receiver. When the FEI block is launched, the frequency error is measured and the Rev 5 - June 2011 DATA DCLK Figure 13. Bit Synchronizer Description Page 31 SX1233 DATASHEET www.semtech.com ...
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... Clear the former AFC correction value, if AfcAutoClearOn = 1 Rev 5 - June 2011 ⎛ ⎞ BR × ------ - = ⎝ ⎠ DEV × = FEI F FeiValue STEP SX1239 in Rx mode 3 Preamble-modulated input signal Signal level > Sensitivity Set FeiStart = 1 No FeiDone = 1 Yes Read FeiValue Figure 14. FEI Process Page 32 SX1233 DATASHEET www.semtech.com ...
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... When temperature is measured, the receiver ADC is used to digitize the sensor response. Most receiver blocks are disabled, and temperature measurement can only be triggered in Standby or Frequency Synthesizer modes. Rev 5 - June 2011 Offset = LowBetaAfcOffset x 488 Hz TX AfcValue Standard AFC AfcLowBetaOn = AfcValue Optimized AFC AfcLowBetaOn = 1 f After AFC Figure 15. Optimized AFC (AfcLowBetaOn=1) Page 33 SX1233 DATASHEET RX & LowBetaAfcOffset f www.semtech.com ...
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... Timeout interrupt is generated TimeoutRssiThresh Tbit after RssiThreshold flag has been raised. This timeout interrupt can be used to warn the companion processor to shut down the receiver and return to a lower power mode. Rev 5 - June 2011 ° -1 C/Lsb ° t t+1 Ambient -40 C Figure 16. Temperature Sensor Response Page 34 SX1233 DATASHEET ° +85 C www.semtech.com ...
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... Carrier frequency of the receiver should be programmed with 40kHz offset from the programmed carrier frequency of transmitter. This offset takes into account the possible +/-15ppm drifts of Crystals. No AFC is needed. Note for both 500 and 600kbps operations, RegTestPll must be set to 0x0C. Rev 5 - June 2011 Page 35 SX1233 DATASHEET www.semtech.com ...
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... Listen Mode Page 36 SX1233 DATASHEET Enabled blocks None Top regulator and crystal oscillator Frequency synthesizer Frequency synthesizer and transmitter Frequency synthesizer and receiver See Listen Mode, section 4.3 = TS_OSC + TS_FS + TS_TR = TS_OSC + TS_FS + TS_RE = TS_OSC + TS_FS + TS_RE_AGC = TS_OSC + TS_FS + TS_RE_AGC&AFC www.semtech.com ...
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... The startup times of the receiver can be calculated from the following: Rev 5 - June 2011 μ × PaRamp 1 μ × Tbit 2 TS_TR 1.25 x PaRamp Analog 0.5 x Tbit (only in FSK group delay mode Figure 17. Tx Startup, FSK and OOK Page 37 SX1233 DATASHEET 1 + × Tbit 2 , Transmission of Packet www.semtech.com ...
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... The LNA gain is adjusted by Carrier Frequency is adjusted the AGC, according to the RSSI result PLL Channel Filter’s DC Cutoff’s AFC Reception of Packet lock group delay group delay Tafc Tpllafc Tcf Tdcc (also denoted TS_AFC in the general specification) (aka TS_RSSI) SX1233 by the AFC www.semtech.com ...
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... Change the carrier frequency in the RegFrf registers (2) Program the SX1233 in FS mode (3) Turn the transceiver back to Rx mode (4) Respect the Rx start procedure, described in section 4.2.4 Note all sequences described above are assuming that the sequencer is turned on (SequencerOff=0 in RegOpMode). Rev 5 - June 2011 Page 39 SX1233 DATASHEET www.semtech.com ...
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... The time during which the receiver is on and waits for a signal is given ListenIdle (denoted t in the following text) are fixed by two parameters from the ListenX = ⋅ t ListenCoef X Listen ListenX Min duration ( ListenCoef = 4 0.26 s Page 40 SX1233 DATASHEET Rx t ListenRx Re solX Max duration ( ListenCoef = 255 ) www.semtech.com time ...
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... Mode. Listen mode stops and must be disabled. Chip stays in Rx mode until PayloadReady or Timeout interrupt occurs. Listen mode then 10 resumes in Idle state. FIFO content is lost at next Rx wakeup. Rev 5 - June 2011 Input Signal Power >= RssiThreshold 0 Required 1 Required Description Page 41 SX1233 DATASHEET SyncAddressMatch Not Required Required www.semtech.com ...
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... For applications enduring large temperature variations, and for which the power supply is never removed, RC calibration can be performed upon user request. RcCalStart in RegOsc1 can be used to trigger this calibration, and the flag RcCalDone will be set automatically when the calibration is over. Rev 5 - June 2011 Idle Rx Idle Rx Idle Rx Page 42 SX1233 DATASHEET Mode Idle Rx www.semtech.com ...
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... Automatic reception (AutoRx) : Mode = Rx, IntermediateMode = Sleep, EnterCondition = CrcOk, ExitCondition = falling edge of FifoNotEmpty Automatic reception of acknowledge (AutoRxAck): Mode = Tx, IntermediateMode = Rx, EnterCondition = PacketSent, ExitCondition = CrcOk ... Rev 5 - June 2011 Intermediate State defined by IntermediateMode EnterCondition Final state defined By Mode in RegOpMode Figure 23. Auto Modes of Packet Handler Page 43 SX1233 DATASHEET ExitCondition www.semtech.com ...
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... Depending on the optional features activated (CRC, AES, etc) the maximum payload length is limited to FIFO size, 255 bytes or unlimited. Each of these data operation modes is described fully in the following sections. Rev 5 - June 2011 CONTROL PACKET FIFO HANDLER (+SR) Page 44 SX1233 DATASHEET DIO0 DIO1 DIO2 DIO3 DIO4 DIO5 SPI NSS SCK MOSI MISO www.semtech.com ...
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... In FIFO mode, if the address was the FIFO address then the bytes will be written / read at the FIFO address. In Burst mode, if the address was not the FIFO address, then it is automatically incremented at each new byte received. Rev 5 - June 2011 Figure 25. SPI Timing Diagram (single access) Page 45 SX1233 DATASHEET www.semtech.com ...
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... PacketSent: PacketSent interrupt source goes high when the SR's last bit has been sent. FifoLevel: Threshold can be programmed by FifoThreshold in RegFifoThresh. Its behavior is illustrated in figure below. Rev 5 - June 2011 byte1 byte0 8 Data Tx/Rx SR (8bits) 1 MSB Figure 26. FIFO and Shift Register (SR) Page 46 SX1233 DATASHEET FIFO LSB www.semtech.com ...
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... Figure 27. FifoLevel IRQ Source Behavior FIFO status Not cleared Not cleared Not cleared To allow the user to write the FIFO in Stdby/Sleep before Tx Cleared Cleared Not cleared To allow the user to read FIFO in Stdby/Sleep mode after Rx Cleared Page 47 SX1233 DATASHEET # of bytes in FIFO Comments www.semtech.com ...
Page 48
... The control block configures and controls the full chip's behavior according to the settings programmed in the configuration registers. 5.3. Digital IO Pins Mapping Six general purpose IO pins are available on the SX1233, and their configuration in Continuous or Packet mode is controlled through RegDioMapping1 and RegDioMapping2. Rev 5 - June 2011 Bit N-1 = Bit N = Sync_value[1] Sync_value[0] Figure 28. Sync Word Recognition Page 48 SX1233 DATASHEET www.semtech.com ...
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... Dclk PllLock TxReady TxReady LowBat LowBat PllLock ModeReady DIO1 DIO0 FifoLevel - - FifoFull - FifoNotEmpty LowBat - - FifoLevel - - FifoFull - FifoNotEmpty LowBat - - FifoLevel - - FifoFull - FifoNotEmpty LowBat PllLock PllLock FifoLevel CrcOk FifoFull PayloadReady FifoNotEmpty SyncAddress Timeout Rssi FifoLevel PacketSent FifoFull TxReady FifoNotEmpty LowBat PllLock PllLock www.semtech.com ...
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... DCLK is required when the modulation shaping is enabled (see section 3.4.5). Rev 5 - June 2011 CONTROL Figure 29. Continuous Mode Conceptual View T_DATA T_DATA Figure 30. Tx Processing in Continuous Mode Page 50 SX1233 DATASHEET DIO0 DIO1/DCLK DIO2/DATA DIO3 DIO4 DIO5 SPI NSS SCK MOSI MISO www.semtech.com ...
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... This simplifies software and reduces uC overhead by performing these repetitive tasks within the RF chip itself. Another important feature is ability to fill and empty the FIFO in Sleep/Stdby mode, ensuring optimum power consumption and adding more flexibility for the software. Rev 5 - June 2011 Figure 31. Rx Processing in Continuous Mode Page 51 SX1233 DATASHEET www.semtech.com ...
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... Preamble (1010...) Sync word (Network ID) Optional Address byte (Node ID) Message data Optional 2-bytes CRC checksum Rev 5 - June 2011 CONTROL PACKET FIFO HANDLER (+SR) Figure 32. Packet Mode Conceptual View Page 52 SX1233 DATASHEET DIO0 DIO1 DIO2 DIO3 DIO4 DIO5 SPI NSS SCK MOSI MISO www.semtech.com ...
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... Figure 33. Fixed Length Packet Format DC free Data encoding CRC checksum calculation Sync Word Length Address bytes byte byte Payload (min 2 bytes) Figure 34. Variable Length Packet Format Page 53 SX1233 DATASHEET CRC 2-bytes AES Enc/Dec Message CRC Up to 255 bytes 2-bytes www.semtech.com ...
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... Optional DC-free encoding of the data (Manchester or whitening) Only the payload (including optional address and length fields) is required to be provided by the user in the FIFO. Rev 5 - June 2011 DC free Data encoding Sync Word Address Message unlimited length byte Payload Figure 35. Unlimited Length Packet Format Page 54 SX1233 DATASHEET www.semtech.com ...
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... AES is the symmetric-key block cipher that provides the cryptographic capabilities to the transceiver. The system proposed can work with 128-bit long fixed keys. The fixed key is stored in a 16-byte write only user configuration register, which retains its value in Sleep mode. Rev 5 - June 2011 Page 55 SX1233 DATASHEET www.semtech.com ...
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... If the address filtering is expected then AddressFiltering must be enabled on the transmitter side as well to prevent address byte to be encrypted. Crc check being performed on encrypted data, CrcOk interrupt will occur "decryption time" before PayloadReady interrupt. Rev 5 - June 2011 Page 56 SX1233 DATASHEET www.semtech.com ...
Page 57
... Every received packet which does not start with this locally configured Sync word is automatically discarded and no interrupt is generated. When the Sync word is detected, payload reception automatically starts and SyncAddressMatch is asserted. Note Sync Word values containing 0x00 byte(s) are forbidden Rev 5 - June 2011 Page 57 SX1233 DATASHEET www.semtech.com ...
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... Please note that in both cases, the two CRC checksum bytes are stripped off by the packet handler and only the payload is made available in the FIFO. The CRC is based on the CCITT polynomial as shown below. This implementation also detects errors due to leading and trailing zeros. Rev 5 - June 2011 Page 58 SX1233 DATASHEET www.semtech.com ...
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... Manchester encoding/decoding is thus made transparent for the user, who still provides/retrieves NRZ data to/from the FIFO. 1/BR RF chips @ BR ... 1 User/NRZ bits ... 1 Manchester OFF User/NRZ bits ... 1 Manchester ON Rev 5 - June 2011 CRC Polynomial = Figure 36. CRC Implementation 1/BR ...Sync Figure 37. Manchester Encoding/Decoding Page 59 DATASHEET Payload... SX1233 X 0 ... t ... ... www.semtech.com ...
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... CRC checksum is then XORed with this random sequence as shown below. The data is de-whitened on the receiver side by XORing with the same random sequence. Payload whitening/de-whitening is thus made transparent for the user, who still provides/retrieves NRZ data to/from the FIFO Rev 5 - June 2011 ran ata Figure 38. Data Whitening Page 60 SX1233 DATASHEET hite ata www.semtech.com X 0 ...
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... Low Battery Indicator Settings 0x92 Listen Mode settings 0xF5 Listen Mode Idle duration 0x20 Listen Mode Rx duration 0x23 Semtech ID relating the silicon revision 0x9F PA selection and Output Power control 0x09 Control of the PA ramp time in FSK mode 0x1A Over Current Protection control 0x40 ...
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... Preamble length, LSB 0x98 Sync Word Recognition control 0x00 0x01 Sync Word bytes, 1 through 8 0x10 Packet mode settings 0x40 Payload length setting 0x00 Node address 0x00 Broadcast address 0x00 Auto modes settings 0x0F 0x8F Fifo threshold, Tx start condition Page 62 SX1233 DATASHEET Description www.semtech.com ...
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... Note - Reset values are automatically refreshed in the chip at Power On Reset - Default values are the Semtech recommended register values, optimizing the device operation - Registers for which the Default value differs from the Reset value are denoted the tables of section 6 Rev 5 - June 2011 ...
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... Data shaping: in FSK shaping 01 Gaussian filter 1.0 10 Gaussian filter 0.5 11 Gaussian filter 0.3 in OOK shaping 01 filtering with f cutoff 10 filtering with f cutoff 11 reserved rw 0x1a MSB of Bit Rate (Chip Rate when Manchester encoding is enabled) Page 64 SX1233 DATASHEET = BR = 2*BR www.semtech.com ...
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... Real-time (not latched) output of the Low Battery detector, when enabled Low Battery detector enable signal 0 LowBat off 1 LowBat on rw 010 Trimming of the LowBat threshold: 000 1.695 V 001 1.764 V 010 1.835 V 011 1.905 V 100 1.976 V 101 2.045 V 110 2.116 V 111 2.185 V Page 65 SX1233 DATASHEET FXOSC ---------------------------------- - = BitRate www.semtech.com ...
Page 66
... Duration of the Rx phase in Listen mode (startup time included, see section 4.2. ListenCoef ListenRx r 0x23 Version code of the chip. Bits 7-4 give the full revision number; bits 3-0 give the metal mask revision number. Page 66 SX1233 DATASHEET ⋅ Re Idle Listen solIdle ⋅ Listen solRx www.semtech.com ...
Page 67
... Enables overload current protection (OCP) for the PA: 0 OCP disabled 1 OCP enabled rw 1010 Trimming of OCP current: × OcpTrim Imax 95 mA OCP by default Page 67 SX1233 DATASHEET ( ) mA www.semtech.com ...
Page 68
... See Table 13 for tabulated values rw 100 DccFreq parameter used during the AFC rw 01 RxBwMant parameter used during the AFC rw 011 * RxBwExp parameter used during the AFC Page 68 SX1233 DATASHEET × 4 RxBw ----------------------------------------- - + 2 DccFreq 2 π 2 × 10 RxBwMant = 24 11 reserved FXOSC + 2 RxBwExp × FXOSC + 3 RxBwExp × www.semtech.com ...
Page 69
... Absolute value of the RSSI in dBm, 0.5dB steps. RSSI = - RssiValue/2 [dBm] Page 69 SX1233 DATASHEET average reserved 1.0 dB 2.0 dB 4.0 dB 6.0 dB 001 once every 2 chips 011 once every 8 chips 101 4 times in each chip 111 16 times in each chip 01 f ≈ chip rate / 8.π ≈ chip rate / 2.π C www.semtech.com ...
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... Please note that in Sleep mode a small delay can be observed between AutoMode interrupt and the corresponding enter/exit condition. r/rwc 0 Set when Sync and Address (if enabled) are detected. Cleared when leaving Rx or FIFO is emptied. This bit is read only in Packet mode, rwc in Continuous mode Page 70 SX1233 DATASHEET www.semtech.com ...
Page 71
... Timeout interrupt is generated TimeoutRxStart *16*T after switching to Rx mode if Rssi interrupt doesn’t occur (i.e. RssiValue > RssiThreshold) 0x00: TimeoutRxStart is disabled rw 0x00 Timeout interrupt is generated TimeoutRssiThresh *16*T after Rssi interrupt if PayloadReady interrupt doesn’t occur. 0x00: TimeoutRssiThresh is disabled Page 71 SX1233 DATASHEET bit bit www.semtech.com ...
Page 72
... Used if SyncOn is set and (SyncSize +1) > 0x01 th 6 byte of Sync word. * Used if SyncOn is set and (SyncSize +1) > 0x01 th 7 byte of Sync word. * Used if SyncOn is set and (SyncSize +1) > 0x01 th 8 byte of Sync word. * Used if SyncOn is set and (SyncSize + Page 72 SX1233 DATASHEET www.semtech.com ...
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... Rising edge of CrcOk or Timeout 100 Rising edge of PayloadReady or Timeout 101 Rising edge of SyncAddress or Timeout 110 Rising edge of PacketSent 111 Rising edge of Timeout rw 00 Intermediate mode: 00 Sleep mode (SLEEP) 01 Standby mode (STDBY) 10 Receiver mode (RX) 11 Transmitter mode (TX) Page 73 SX1233 DATASHEET www.semtech.com ...
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... Page 74 SX1233 DATASHEET ) / BitRate otherwise www.semtech.com ...
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... Wider for Bit Rates up to 600 kbps rw 0x30 Fading Margin Improvement, refer to 3.5.4 * 0x00 Normal mode 0x20 Improved margin, use if AfcLowBetaOn=1 0x30 Improved margin, use if AfcLowBetaOn=0 rw 0x00 AFC offset set for low modulation index systems, used if AfcLowBetaOn=1 . Offset = LowBetaAfcOffset x 488 Hz Page 75 SX1233 DATASHEET www.semtech.com ...
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... Please note that any CLKOUT activity can also be used to detect that the chip is ready. Rev 5 - June 2011 Conditions On each pin XTA and XTB Undefined Wait for Chip is ready from 10 ms this point on Figure 39. POR Timing Diagram Page 76 SX1233 DATASHEET Min Typ Max Unit MHz - 30 140 ohms - 2 www.semtech.com ...
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... VDD. 7.3. Reference Design Please contact your Semtech representative for evaluation tools, reference designs and design assistance. Note that all schematics shown in this section are full schematics, listing ALL required components, including decoupling capacitors. ...
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... MHz 433 MHz 868 MHz 100 1.5 nH 1 Page 78 SX1233 DATASHEET 915 MHz Type X7R X7R COG 3 Wirewound air core 6 multilayer* 6.8 nH 4 COG 6 5.6 pF 915 MHz Type X7R X7R COG 2 Wirewound air core 5 multilayer (1) 5 www.semtech.com ...
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... C14 C15 Notes - Complete details on selected components are available in the reference design package, downloadable from the Semtech website - (1) Inductor values may change when using multilayer type components - (2) An additional DC-cut capacitor (typ. 47pF) might be required with this matching topology and certain RF ...
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... A2 b 0.25 0.30 0.35 D 4.90 5.00 5.10 D1 3.20 3.25 3.30 E 4.90 5.00 5.10 E1 3.20 3.25 3.30 e 0.65 BSC L 0.35 0.40 0. aaa 0.08 bbb 0.10 SEATING PLANE DIMENSIONS DIM MILLIMETERS (4.90 4.10 H 3.30 K 3.30 P 0.65 X 0.35 Y 0.80 Z 5.70 SX1233 DATASHEET www.semtech.com ...
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... The thermal impedance of this package is: Theta ja = 23.8° C/W typ., calculated from a package in still air 4-layer FR4 PCB, as per the Jedec standard. 8.4. Tape & Reel Specification Note Single Sprocket holes Rev 5 - June 2011 Figure 45. Tape & Reel Specification Page 81 SX1233 DATASHEET www.semtech.com ...
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... ContinuousDagc This register enables a functionnality that is only available in the silicon version V2c. Rev 5 - June 2011 Lot Codes (see Figure 3) W6A114.0A ¦ W0N382.00 W0N386.00 ¦ W0P051.00 W0S934.01 and all others Page 82 SX1233 DATASHEET Comment Limited supply Running production www.semtech.com ...
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... June 2011 State all Blocking and AM Rejection figures in dB Adjust band coverage to 431-510 MHz Provide table with Dcc cutoff frequencies Add note on the behavior of PLL Lock indicator for wideband modulations Add Bill Of Material information Rev 5 - June 2011 Comment Page 83 SX1233 DATASHEET www.semtech.com ...
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... No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified range ...