TC4423AVMF713 Microchip Technology, TC4423AVMF713 Datasheet - Page 9

• Manufacturer Part Number: TC4423AVMF713
• Description: IC,Dual MOSFET Driver,LLCC,8PIN,PLASTIC
• Manufacturer: Microchip Technology
• Type: Low Sider

Specifications of TC4423AVMF713

• Configuration: Low-Side
• Input Type: Inverting
• Delay Time: 40ns
• Current - Peak: 4.5A
• Number Of Configurations: 2
• Number Of Outputs: 2
• Voltage - Supply: 4.5 V ~ 18 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-DFN
• Rise Time: 21 ns
• Fall Time: 21 ns
• Supply Voltage (min): 4.5 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Drivers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• High Side Voltage - Max (bootstrap): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.0
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
3.1
Inputs A and B are TTL/CMOS compatible inputs that
control outputs A and B, respectively. These inputs
have 300 mV of hysteresis between the high and low
input levels, allowing them to be driven from slow rising
and falling signals, and to provide noise immunity.
3.2
Outputs A and B are CMOS push-pull outputs that are
capable of sourcing and sinking 3A peaks of current
(V
gate of the external MOSFET will stay in the intended
state even during large transients. These outputs also
have a reverse current latch-up rating of 1.5A.
3.3
V
has a voltage range of 4.5V to 18V. This input must be
decoupled to ground with a local ceramic capacitor.
This bypass capacitor provides a localized low-
impedance path for the peak currents that are to be
provided to the load.
© 2007 Microchip Technology Inc.
Note 1:
DD
8-Pin PDIP
DD
is the bias supply input for the MOSFET driver and
= 18V). The low output impedance ensures the
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1
2
3
4
5
6
7
8
PIN DESCRIPTIONS
Inputs A and B
Outputs A and B
Supply Input (V
Duplicate pins must be connected for proper operation.
PIN FUNCTION TABLE
8-Pin
DFN
PAD
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1
2
3
4
5
6
7
8
DD
(Wide)
16-Pin
SOIC
)
10
11
12
13
14
15
16
—
1
2
3
4
5
6
7
8
9
TC4423A/TC4424A/TC4425A
Symbol
OUT B
OUT B
OUT A
OUT A
(1)
GND
GND
IN A
IN B
V
V
NC
NC
NC
NC
NC
NC
NC
DD
DD
No connection
Input A
No connection
Ground
Ground
No connection
Input B
No connection
No connection
Output B
Output B
Supply input
Supply input
Output A
Output A
No connection
Exposed Metal Pad
3.4
Ground is the device return pin. The ground pin should
have a low-impedance connection to the bias supply
source return. High peak currents will flow out the
ground pin when the capacitive load is being
discharged.
3.5
The exposed metal pad of the DFN package is not
internally connected to any potential. Therefore, this
pad can be connected to a ground plane or other
copper plane on a printed circuit board to aid in heat
removal from the package.
Ground (GND)
Exposed Metal Pad
Description
DS21998B-page 9