AM79C973BKD AMD (ADVANCED MICRO DEVICES), AM79C973BKD Datasheet - Page 114

• Manufacturer Part Number: AM79C973BKD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKD

• Lead Free Status / RoHS Status: Compliant

ler within AMD’s product line. The Am79C973/
Am79C975 Device ID is 2000h. Note that this Device
ID is not the same as the Part number in CSR88 and
CSR89. The Device ID is assigned by AMD. The De-
vice ID is the same as the PCnet-PCI II (Am79C970A)
and PCnet-FAST (Am79C971) devices.
The PCI Device ID register is located at offset 02h in
the PCI Configuration Space. It is read only.
PCI Command Register
Offset 04h
The PCI Command register is a 16-bit register used to
control the gross functionality of the Am79C973/
Am79C975 controller. It controls the Am79C973/
Am79C975 controller’s ability to generate and respond
to PCI bus cycles. To logically disconnect the
Am79C973/Am79C975 device from all PCI bus cycles
except configuration cycles, a value of 0 should be writ-
ten to this register.
The PCI Command register is located at offset 04h in
the PCI Configuration Space. It is read and written by
the host.
Bit
15-10
9
8
7
6
114
Name
RES
FBTBEN
SERREN
RES
PERREN
ros; write operations have no ef-
fect.
as zero; write operations have no
effect.
Am79C975 controller will not
generate Fast Back-to-Back cy-
cles.
sertion of the SERR pin. SERR is
disabled
cleared. SERR will be asserted
on detection of an address parity
error and if both SERREN and
PERREN (bit 6 of this register)
are set.
H_RESET and is not effected by
S_RESET or by setting the STOP
bit.
ros; write operations have no ef-
fect.
Enables the parity error response
functions. When PERREN is 0
and the Am79C973/Am79C975
Description
Reserved locations. Read as ze-
Fast Back-to-Back Enable. Read
SERR Enable. Controls the as-
SERREN
Reserved location. Read as ze-
Parity Error Response Enable.
when
The
is
SERREN
cleared
Am79C973/
P R E L I M I N A R Y
Am79C973/Am79C975
by
is
5
4
3
2
1
VGASNOOP
MWIEN
SCYCEN
BMEN
MEMEN
controller detects a parity error, it
only sets the Detected Parity Er-
ror bit in the PCI Status register.
When
Am79C973/Am79C975 controller
asserts PERR on the detection of
a data parity error. It also sets the
DATAPERR bit (PCI Status reg-
ister, bit 8), when the data parity
error occurred during a master
cycle. PERREN also enables re-
porting address parity errors
through the SERR pin and the
SERR bit in the PCI Status regis-
ter.
PERREN
H_RESET and is not affected by
S_RESET or by setting the STOP
bit.
VGA Palette Snoop. Read as ze-
ro; write operations have no ef-
fect.
Memory Write and Invalidate Cy-
cle Enable. Read as zero; write
operations have no effect. The
Am79C973/Am79C975 controller
only generates Memory Write cy-
cles.
Special Cycle Enable. Read as
zero; write operations have no ef-
fect. The Am79C973/Am79C975
controller ignores all Special Cy-
cle operations.
Bus
BMEN enables the Am79C973/
Am79C975 controller to become
a bus master on the PCI bus. The
host must set BMEN before set-
ting the INIT or STRT bit in CSR0
of
controller.
BMEN is cleared by H_RESET
and is not effected by S_RESET
or by setting the STOP bit.
Memory Space Access Enable.
The Am79C973/Am79C975 con-
troller will ignore all memory ac-
cesses when MEMEN is cleared.
The host must set MEMEN be-
fore the first memory access to
the device.
the
Master
PERREN
Am79C973/Am79C975
is
Enable.
cleared
is
1,
Setting
the
by