ADV7190KST Analog Devices Inc, ADV7190KST Datasheet - Page 30

• Manufacturer Part Number: ADV7190KST
• Manufacturer: Analog Devices Inc

Specifications of ADV7190KST

• Number Of Dac's: 6
• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Not Compliant

ADV7190/ADV7191
MODE REGISTER 2
MR2 (MR27–MR20)
(Address (SR4–SR0) = 02H)
Mode Register 2 is an 8-bit-wide register.
Figure 52 shows the various operations under the control of Mode
Register.
MR2 BIT DESCRIPTION— RGB/YUV Control (MR20)
This bit enables the output from the small or large DACs to be
set to YUV or RGB output video standard.
DAC Output Control (MR21)
This bit controls the output from DACs A, B, and C. When this
bit is set to 1, Composite, Luma, and Chroma Signals are out-
put from DACs A, B, and C (respectively). When this bit is set
to 0, RGB or YUV may be output from these DACs.
SCART Enable Control (MR22)
This bit is used to switch the DAC outputs from SCART to a
EUROSCART configuration. A complete table of all DAC
output configurations is shown in Table III.
Pedestal Control (MR23)
This bit specifies whether a pedestal is to be generated on the
NTSC composite video signal. This bit is invalid when the device
is configured in PAL mode.
Square Pixel Control (MR24)
This bit is used to set up square pixel mode. This is available in
Slave Mode only. For NTSC, a 24.5454 MHz clock must be
supplied. For PAL, a 29.5 MHz clock must be supplied. Square
pixel operation is not available in 4¥ Oversampling mode.
SCART
MR22
0
0
0
0
1
1
1
1
DAC O/P
MR21
0
0
1
1
0
0
1
1
MR27
0
1
SLEEP MODE
CONTROL
RGB/YUV
MR20
0
1
0
1
0
1
0
1
DISABLE
ENABLE
MR27
MR26
VALID CONTROL
0
1
PIXEL DATA
DISABLE
ENABLE
MR26
Table III. DAC Output Configuration Matrix
MR25
DAC A
G
Y
CVBS
CVBS
CVBS
CVBS
CVBS
CVBS
STANDARD I
0
1
Figure 52. Mode Register 2 (MR2)
CONTROL
DISABLE
ENABLE
MR25
MR24
2
SQUARE PIXEL
0
1
C
CONTROL
DISABLE
ENABLE
DAC B
B
U
LUMA
LUMA
B
U
LUMA
LUMA
MR24
MR23
–30–
0
1
PEDESTAL
CONTROL
PEDESTAL OFF
PEDESTAL ON
Standard I
This bit controls the video standard used by the ADV7190/
ADV7191. When this bit is set to 1 the video standard as
programmed in Output Video Standard Selection (MR00,
MR01). When MR25 is set to 0, the ADV7190/ADV7191 is
forced into the standard selected by the NTSC_PAL pin. When
NTSC_PAL is low the standard is NTSC, when the NTSC_PAL
pin is high, the standard is PAL.
Pixel Data Valid Control (MR26)
After resetting the device, this bit has the value 0 and the pixel
data input to the encoder is blanked such that a black screen is
output from the DACs. The ADV7190/ADV7191 will be set
to Master Mode timing. When this bit is set to 1 by the user
(via the I
reverts to the Timing Mode defined by Timing Register 0.
Sleep Mode Control (MR27)
When this bit is set (1), Sleep Mode is enabled. With this mode
enabled, the ADV7190/ADV7191 current consumption is reduced
to less than 1 mA. The I
from when the ADV7190/ADV7191 is in Sleep Mode.
When the device is in Sleep Mode and 0 is written to MR27, the
ADV7190/ADV7191 will come out of Sleep Mode and resume
normal operation. Also, if a RESET is applied during Sleep
Mode, the ADV7190/ADV7191 will come out of Sleep Mode
and resume normal operation.
For this to operate, Power Up in Sleep Mode Control has to be
enabled (MR60 = 0), otherwise Sleep Mode is controlled by
the PAL_NTSC and SCRESET/RTC/TR pins.
MR23
MR22
DAC C
R
V
CHROMA
CHROMA
R
V
CHROMA
CHROMA
SCART ENABLE
0
1
CONTROL
2
C), pixel data passes to the pins and the encoder
DISABLE
ENABLE
MR22
2
C Control (MR25)
MR21
0
1
RGB/YUV/COMP
COMP/LUMA/CHROMA
MR21
DAC OUTPUT
CONTROL
2
DAC D
CVBS
CVBS
G
Y
G
Y
G
Y
C registers can be written to and read
MR20
0
1
CONTROL
RGB/YUV
RGB OUTPUT
YUV OUTPUT
MR20
DAC E
LUMA
LUMA
B
U
LUMA
LUMA
B
U
DAC F
CHROMA
CHROMA
R
V
CHROMA
CHROMA
R
V
REV. B