LTC1065CSW#TRMPBF Linear Technology, LTC1065CSW#TRMPBF Datasheet - Page 7

• Manufacturer Part Number: LTC1065CSW#TRMPBF
• Manufacturer: Linear Technology

Specifications of LTC1065CSW#TRMPBF

• Architecture: Switched Capacitor
• Order Filter (max): 5th
• Single Supply Voltage (typ): 5/9/12/15V
• Dual Supply Voltage (typ): ±5V
• Power Supply Requirement: Single/Dual
• Single Supply Voltage (min): 4.75V
• Single Supply Voltage (max): 16V
• Dual Supply Voltage (min): ±2.375V
• Dual Supply Voltage (max): ±8V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Package Type: SOIC W
• Filter Type: Low Pass Filter
• Lead Free Status / RoHS Status: Compliant

PI FU CTIO S
Input Pin (Pin 1, N Package)
Pin 1 is the filter input and it is connected to an internal
switched-capacitor resistor. If the input pin is left floating,
the filter output will saturate. The DC input impedance of
pin 1 is very high; with ±5V supplies and 1MHz clock, the
DC input impedance is typically 1GΩ. A resistor R
series with the input pin will not alter the value of the filter’s
DC output offset (Figure 1). R
to a maximum value (Table 1), otherwise the filter’s pass-
band will be affected. Refer to the Applications Information
section for more details.
Table 1. R
Output Pin (Pin 7, N Package)
Pin 7 is the filter output. This pin can typically source over
20mA and sink 2mA. Pin 7 should not drive long coax
cables, otherwise the filter’s total harmonic distortion will
degrade. The maximum load the filter output can drive and
still maintain the distortion levels, shown in the Typical
Performance Characteristics, is 20k.
Clock Input Pin (Pin 5, N Package)
An external clock, when applied to pin 5, tunes the filter
cutoff frequency. The clock-to-cutoff frequency ratio is
f
f
f
f
f
f
U
CLK
CLK
CLK
CLK
CLK
CLK
= 4MHz
= 3MHz
= 2MHz
= 1MHz
= 500kHz
= 100kHz
IN(MAX)
U
V
IN
vs Clock and Power Supply
R
V
IN
–
U
V
1
2
3
4
S
1.82k
3.01k
4.32k
9.09k
17.8k
95.3k
= ±7.5V
Figure 1.
LTC1065
IN
should however, be limited
8
7
6
5
V
R
S
IN(MAX)
2.49k
3.65k
8.25k
16.9k
90.9k
V
V
f
1065 F01
CLK
= ±5V
OUT
+
–
V
S
2.37k
16.9k
90.9k
= ±2.5V
7.5k
–
–
IN
in
100:1. The high (V
threshold levels are illustrated in Table 2. Square wave
clocks with duty cycles between 30% and 50% are strongly
recommended. Sinewave clocks are not recommended.
Table 2. Clock Pin Threshold Levels
Clock Output Pin (Pin 4, N Package)
Any external clock applied to the clock input pin appears
at the clock output pin. The duty cycle of the clock output
equals the duty cycle of the external clock applied to the
clock input pin. The clock output pin swings to the power
supply rails. When the LTC1065 is used in a self-clocking
mode, the clock of the internal oscillator appears at the
clock output pin with a 30% duty cycle. The clock output
pin can be used to drive other LTC1065s or other ICs. The
maximum capacitance, C
drive is illustrated in Figure 2.
Figure 2. Maximum Load Capacitance at the Clock Output Pin
POWER SUPPLY
V
V
V
V
V
V
V
S
S
S
S
S
S
S
= ±2.5V
= ±5V
= ±7.5V
= ±8V
= 5V, 0V
= 12V, 0V
=15V, 0V
200
180
160
140
120
100
80
60
40
20
0
1
V
V
V
S
S
S
= ±2.5V
= ±5V
= ±7.5V
HIGH
CLOCK FREQUENCY (MHz)
2
) and low (V
L(MAX)
V
1.5V
4.5V
4.8V
9.6V
12V
3
HIGH
3V
4V
, the clock output pin can
4
5 6 7 8 9
T
A
= 25°C
LOW
1065 F02
LTC1065
) clock logic
10
V
0.5V
1.5V
1.6V
7.2V
LOW
1V
3V
9V
1065fb
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