AD73422BB-80 Analog Devices Inc, AD73422BB-80 Datasheet - Page 2

• Manufacturer Part Number: AD73422BB-80
• Manufacturer: Analog Devices Inc

Specifications of AD73422BB-80

• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Package Type: BGA
• Lead Free Status / RoHS Status: Not Compliant

Parameter
AFE SECTION
REFERENCE
INPUT AMPLIFIER
ANALOG GAIN TAP
ADC SPECIFICATIONS
DIGITAL GAIN TAP
AD73422–SPECIFICATIONS
REFCAP
REFOUT
Offset
Maximum Output Swing
Feedback Resistance
Feedback Capacitance
Gain at Maximum Setting
Gain at Minimum Setting
Gain Resolution
Gain Accuracy
Settling Time
Delay
Maximum Input Range at VIN
Nominal Reference Level at VIN
Absolute Gain
Gain Tracking Error
Signal to (Noise + Distortion)
Total Harmonic Distortion
Intermodulation Distortion
Idle Channel Noise
Crosstalk, ADC-to-DAC
DC Offset
Power Supply Rejection
Group Delay
Input Resistance at PGA
Gain at Maximum Setting
Gain at Minimum Setting
Gain Resolution
Delay
Settling Time
Absolute Voltage, V
REFCAP TC
Typical Output Impedance
Absolute Voltage, V
Minimum Load Resistance
Maximum Load Capacitance
(0 dBm0)
PGA = 0 dB
PGA = 38 dB
PGA = 0 dB
PGA = 38 dB
PGA = 0 dB
PGA = 38 dB
ADC-to-ADC
4, 5
REFCAP
REFOUT
2, 4, 6
2, 3
Min
1.125 1.25
1.08
1
–0.5
72
55
–30
(AVDD = DVDD = VDD = +3 V to 3.6 V; DGND = AGND = 0 V, f
f
SAMP
= 64 kHz; T
–100
Typ
50
130
1.2
± 1.0
1.578
50
100
+1
–1
5
± 1.0
1.0
0.5
1.578
–2.85
1.0954
–6.02
0.4
–0.7
± 0.1
78
78
57
56
–84
–70
–65
–71
–100
–70
+10
–65
25
20
+1
–1
16
25
100
–2–
A
Max
1.375
1.32
100
+1.2
–73
+45
= T
MIN
to T
V
%
V p-p
dBm
dB
dB
dB
dB
dB
dB
mV
ms
Units
V
ppm/°C
Ω
V
kΩ
pF
mV
kΩ
pF
Bits
ms
ms
V p-p
dBm
dB
dB
dB
dB
dB
dBm0
dB
dB
dB
µs
kΩ
Bits
ms
MAX
, unless otherwise noted.)
ADC1 Input Level: 1.0 kHz, 0 dBm0
Test Conditions
0.1 µF Capacitor Required from
REFCAP to AGND2
Unloaded
Max Output Swing = (1.578/1.25) ×
V
f
Gain Step Size = 0.0625
Output Unloaded
Tap Gain Change of –FS to +FS
Measured Differentially.
Max Input = (1.578/1.25) × V
Measured Differentially
1.0 kHz, 0 dBm0
1.0 kHz, 0 dBm0
1.0 kHz, +3 dBm0 to –50 dBm0
300 Hz to 3400 Hz; f
300 Hz to 3400 Hz; f
0 Hz to f
300 Hz to 3400 Hz; f
300 Hz to 3400 Hz; f
300 Hz to 3400 Hz; f
PGA = 0 dB
PGA = 0 dB
ADC Input Level: 1.0 kHz, 0 dBm0
DAC Input at Idle
ADC2 Input at Idle. Input Amps Bypassed
Input Amplifiers Included in Input
Channel
PGA = 0 dB
Input Signal Level at AVDD and DVDD
Pins: 1.0 kHz, 100 mV p-p Sine Wave
DMCLK = 16.384 MHz; Input
Amplifiers Bypassed and AGT Off
Tested to 5 MSBs of Settings
Includes DAC Delay
Tap Gain Change from –FS to +FS;
Includes DAC Settling Time
C
REFCAP
= 32 kHz
SAMP
/2; f
SAMP
DMCLK
SAMP
SAMP
SAMP
SAMP
SAMP
= 64 kHz
= 16.384 MHz,
= 8 kHz
= 64 kHz
= 64 kHz
= 64 kHz
= 64 kHz
REFCAP
REV. 0