AD73411BB-40 Analog Devices Inc, AD73411BB-40 Datasheet - Page 24

• Manufacturer Part Number: AD73411BB-40
• Manufacturer: Analog Devices Inc

Specifications of AD73411BB-40

• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Package Type: BGA
• Lead Free Status / RoHS Status: Not Compliant

AD73411
are twelve levels deep to allow interrupt, loop, and subroutine
nesting. The following instructions allow global enable or dis-
able servicing of the interrupts (including power-down), regardless
of the state of IMASK. Disabling the interrupts does not affect
serial port autobuffering or DMA.
ENA INTS;
DIS INTS;
When the processor is reset, interrupt servicing is enabled.
LOW-POWER OPERATION
The AD73411 has three low-power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. These modes are:
• Power-Down
• Idle
• Slow Idle
The CLKOUT pin may also be disabled to reduce external
power dissipation.
Power-Down
The AD73411 processor has a low-power feature that lets the
processor enter a very low-power dormant state through hard-
ware or software control. Here is a brief list of power-down
features. Refer to the ADSP-2100 Family User’s Manual, Third
Edition, “System Interface” chapter, for detailed information
about the power-down feature.
• Quick recovery from power-down. The processor begins
• Support for an externally generated TTL or CMOS proces-
• Support for crystal operation includes disabling the oscillator
• Power-down is initiated by either the power-down pin (PWD)
• Context clear/save control allows the processor to continue
• The RESET pin also can be used to terminate power-down.
• Power-down acknowledge pin indicates when the processor
Idle
When the AD73411 is in the Idle Mode, the processor waits
indefinitely in a low power state until an interrupt occurs. When
an unmasked interrupt occurs, it is serviced; execution then
continues with the instruction following the IDLE instruction.
In Idle Mode IDMA, BDMA, and Autobuffer Cycle steals still
occur.
Slow Idle
The IDLE instruction on the AD73411 slows the processor’s
internal clock signal, further reducing power consumption. The
reduced clock frequency, a programmable fraction of the normal
executing instructions in as few as 400 CLKIN cycles.
sor clock. The external clock can continue running during
power-down without affecting the 400 CLKIN cycle recovery.
to save power (the processor automatically waits 4096 CLKIN
cycles for the crystal oscillator to start and stabilize), and
letting the oscillator run to allow 400 CLKIN cycle startup.
or the software power-down force bit. Interrupt support
allows an unlimited number of instructions to be executed
before optionally powering down. The power-down interrupt
also can be used as a nonmaskable, edge-sensitive interrupt.
where it left off or start with a clean context when leaving the
power-down state.
has entered power-down.
clock rate, is specified by a selectable divisor given in the IDLE
instruction. The format of the instruction is
where n = 16, 32, 64, or 128. This instruction keeps the processor
fully functional, but operating at the slower clock rate. While it
is in this state, the processor’s other internal clock signals, such
as SCLK, CLKOUT, and Timer Clock, are reduced by the same
ratio. The default form of the instruction, when no clock divisor
is given, is the standard IDLE instruction.
When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to
incoming interrupts. The one-cycle response time of the standard
idle state is increased by n, the clock divisor. When an enabled
interrupt is received, the AD73411 will remain in the idle state
for up to a maximum of n processor cycles (n = 16, 32, 64, or 128)
before resuming normal operation.
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
rate faster than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
SYSTEM INTERFACE
Figure 13 shows a typical basic system configuration with the
AD73411, two serial devices, a byte-wide EPROM, and
optional external program and data overlay memories (mode
selectable). Programmable wait state generation allows the proces-
sor to connect easily to slow peripheral devices. The AD73411 also
provides four external interrupts and two serial ports or six
external interrupts and one serial port. Host Memory Mode allows
access to the full external data bus, but limits addressing to a
single address bit (A0). Additional system peripherals can be
added in this mode through the use of external hardware to
generate and latch address signals.
Clock Signals
The AD73411 can be clocked by either a crystal or a TTL-
compatible clock signal.
The CLKIN input cannot be halted, changed during opera-
tion, or operated below the specified frequency during normal
operation. The only exception is while the processor is in the
power-down state. For detailed information on this power-down
feature, refer to Chapter 9, ADSP-2100 Family User’s Manual,
Third Edition.
If an external clock is used, it should be a TTL-compatible signal
running at half the instruction rate. The signal is connected to
the processor’s CLKIN input. When an external clock is used,
the XTAL input must be left unconnected.
The AD73411 uses an input clock with a frequency equal to half
the instruction rate; a 26.00 MHz input clock yields a 19 ns
processor cycle (which is equivalent to 52 MHz). Normally,
instructions are executed in a single processor cycle. All device
timing is relative to the internal instruction clock rate, which is
indicated by the CLKOUT signal when enabled.
IDLE (n);