XC2V1000-4FGG456C Xilinx Inc, XC2V1000-4FGG456C Datasheet - Page 93

• Manufacturer Part Number: XC2V1000-4FGG456C
• Description: FPGA Virtex-II™ Family 1M Gates 11520 Cells 650MHz 0.15um/0.12um (CMOS) Technology 1.5V 456-Pin FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-IIr

Specifications of XC2V1000-4FGG456C

• Package: 456FBGA
• Family Name: Virtex-II™
• Device Logic Units: 11520
• Device System Gates: 1000000
• Number Of Registers: 10240
• Maximum Internal Frequency: 650 MHz
• Typical Operating Supply Voltage: 1.5 V
• Maximum Number Of User I/os: 324
• Ram Bits: 737280
• Number Of Labs/clbs: 1280
• Total Ram Bits: 737280
• Number Of I /o: 324
• Number Of Gates: 1000000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 456-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1346

DS031-4 (v3.5) November 5, 2007
This document provides Virtex-II™ Device/Package Combi-
nations, Maximum I/Os Available, and Virtex-II Pin Defini-
tions, followed by pinout tables for the following packages:
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•
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Virtex-II Device/Package Combinations and Maximum I/Os Available
Wire-bond and flip-chip packages are available.
Table 2
wire-bond and flip-chip packages, respectively.
Table 3
device/package combinations.
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Table 1: Wire-Bond Packages Information
Table 2: Flip-Chip Packages Information
© 2000–2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
DS031-4 (v3.5) November 5, 2007
Product Specification
Notes:
1. Wire-bond packages include FGGnnn Pb-free versions. See
Pitch (mm)
Size (mm)
I/Os
Pitch (mm)
Size (mm)
I/Os
CS144/CSG144 Chip-Scale BGA Package
FG256/FGG256 Fine-Pitch BGA Package
FG456/FGG456 Fine-Pitch BGA Package
FG676/FGG676 Fine-Pitch BGA Package
BG575/BGG575 Standard BGA Package
CS denotes wire-bond chip-scale ball grid array (BGA)
(0.80 mm pitch).
CSG denotes Pb-free wire-bond chip-scale ball grid
array (BGA) (0.80 mm pitch).
FG denotes wire-bond fine-pitch BGA (1.00 mm pitch).
Package
Package
show the maximum number of user I/Os possible in
shows the number of user I/Os available for all
(1)
CSG144
CS144/
12 x 12
0.80
92
R
31 x 31
FF896
1.00
624
2
2
6
FGG256
FG256/
17 x 17
1.00
172
Table 1
www.xilinx.com
and
FF1152
35 x 35
1.00
824
Virtex-II Ordering Examples (Module
FGG456
FG456/
23 x 23
1.00
324
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For device pinout diagrams and layout guidelines, refer to
the
pinout files are also available for download from the Xilinx
website (
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The number of I/Os per package include all user I/Os except
the 15 control pins (CCLK, DONE, M0, M1, M2, PROG_B,
PWRDWN_B, TCK, TDI, TDO, TMS, HSWAP_EN, DXN,
DXP, AND RSVD).
BG728/BGG728 Standard BGA Package
FF896 Flip-Chip Fine-Pitch BGA Package
FF1152 Flip-Chip Fine-Pitch BGA Package
FF1517 Flip-Chip Fine-Pitch BGA Package
BF957 Flip-Chip BGA Package
FGG denotes Pb-free wire-bond fine-pitch BGA (1.00
mm pitch).
BG denotes standard BGA (1.27 mm pitch).
BGG denotes Pb-free standard BGA (1.27 mm pitch).
FF denotes flip-chip fine-pitch BGA (1.00 mm pitch).
BF denotes flip-chip BGA (1.27 mm pitch).
Virtex-II Platform FPGA User Guide
www.xilinx.com
FGG676
FG676/
27 x 27
Virtex-II Platform FPGAs:
1.00
484
FF1517
40 x 40
1,108
1.00
).
Pinout Information
1).
BGG575
BG575/
31 x 31
1.27
408
Product Specification
. ASCII package
40 x 40
BF957
1.27
684
BGG728
BG728/
Module 4 of 4
35 x 35
1.27
516
1