XC3S500E-4FT256I Xilinx Inc, XC3S500E-4FT256I Datasheet - Page 56

• Manufacturer Part Number: XC3S500E-4FT256I
• Description: FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 256-Pin FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S500E-4FT256I

• Package: 256FTBGA
• Family Name: Spartan®-3E
• Device Logic Cells: 10476
• Device Logic Units: 1164
• Device System Gates: 500000
• Number Of Registers: 9312
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 190
• Ram Bits: 368640
• Number Of Logic Elements/cells: 10476
• Number Of Labs/clbs: 1164
• Total Ram Bits: 368640
• Number Of I /o: 190
• Number Of Gates: 500000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Functional Description
FIXED Phase Shift Mode
The FIXED phase shift mode shifts the DCM outputs by a
fixed amount (T
PHASE_SHIFT attribute. The PHASE_SHIFT value (shown
as P in
+255. PHASE_SHIFT specifies a phase shift delay as a
fraction of the T
between ISE 8.1, Service Pack 3 and prior software ver-
sions, as described below.
Design Note
Prior to ISE 8.1i, Service Pack 3, the FIXED phase shift fea-
ture operated differently than the Spartan-3 DCM design
primitive and simulation model. Designs using software
prior to ISE 8.1i, Service Pack 3 require recompilation using
the latest ISE software release. The following Answer
Record contains additional information:
http://www.xilinx.com/support/answers/23153.htm.
FIXED Phase Shift using ISE 8.1i, Service Pack 3 and
later: See
shift range of –360
the Spartan-3 DCM design primitive and simulation model.
56
Figure
a. CLKOUT_PHASE_SHIFT = NONE
b. CLKOUT_PHASE_SHIFT = FIXED
Equation
t
PS
Figure 44: NONE and FIXED Phase Shifter Waveforms (ISE 8.1i, Service Pack 3 and later)
44) must be an integer ranging from –255 to
=
CLKIN.
⎛
⎝
PS
PHASESHIFT
----------------------------------------
°
), controlled by the user-specified
2. The value corresponds to a phase
to +360
(via CLK0 or CLK2X feedback)
The phase shift behavior is different
(via CLK0 or CLK2X feedback)
Shift Range over all P Values:
256
°
, which matches behavior of
⎞
⎠
•
T
CLKIN
CLKIN
CLKFB
CLKIN
CLKFB
–255
www.xilinx.com
Eq. 2
FIXED Phase Shift prior to ISE 8.1i, Service Pack 3: See
Equation
–180
tan-3 DCM design primitive and simulation model. Designs
created prior to ISE 8.1i, Service Pack 3 must be recom-
piled using the most recent ISE development software.
When the PHASE_SHIFT value is zero, CLKFB and CLKIN
are in phase, the same as when the PS unit is disabled.
When the PHASE_SHIFT value is positive, the DCM out-
puts are shifted later in time with respect to CLKIN input.
When the attribute value is negative, the DCM outputs are
shifted earlier in time with respect to CLKIN.
Figure 44b
CLKIN in the Fixed Phase mode. In the Fixed Phase mode,
the PSEN, PSCLK, and PSINCDEC inputs are not used
and must be tied to GND.
Equation 2
mode. The VARIABLE phase shift mode operates differ-
ently.
°
to +180
3. The value corresponds to a phase shift range of
0
256
t
illustrates the relationship between CLKFB and
or
P
PS
Equation 3
* T
°
=
CLKIN
degrees, which is different from the Spar-
⎛
⎝
PHASESHIFT
----------------------------------------
512
applies only to FIXED phase shift
+255
DS312-2 (v3.8) August 26, 2009
⎞
⎠
•
T
CLKIN
DS312-2_61_021606
Product Specification
Eq. 3
R