XC5VLX50T-2FFG665C Xilinx Inc, XC5VLX50T-2FFG665C Datasheet - Page 31

FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA

XC5VLX50T-2FFG665C

Manufacturer Part Number
XC5VLX50T-2FFG665C
Description
FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX50T-2FFG665C

Package
665FCBGA
Family Name
Virtex®-5
Device Logic Units
46080
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
360
Ram Bits
2211840
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC5VLX50T-2FFG665C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VLX50T-2FFG665C
Manufacturer:
XILINX
0
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Table 1-4
Table 1-4: BUFGCTRL Attributes
BUFG
BUFG is simply a clock buffer with one clock input and one clock output. This primitive is
based on BUFGCTRL with some pins connected to logic High or Low.
the relationship of BUFG and BUFGCTRL. A LOC constraint is available for BUFG.
X-Ref Target - Figure 1-3
The output follows the input as shown in the timing diagram in
X-Ref Target - Figure 1-4
Notes:
1. Both PRESELECT attributes cannot be TRUE at the same time.
2. The LOC constraint is available.
INIT_OUT
PRESELECT_I0
PRESELECT_I1
Attribute Name
summarizes the attributes for the BUFGCTRL primitive.
BUFG(O)
I
BUFG(I)
Initializes the BUFGCTRL output to the specified
value after configuration. Sets the positive or
negative edge behavior. Sets the output level when
changing clock selection.
If TRUE, BUFGCTRL output uses the I0 input after
configuration
If TRUE, BUFGCTRL output uses the I1 input after
configuration
www.xilinx.com
BUFG
Figure 1-4: BUFG Timing Diagram
Figure 1-3: BUFG as BUFGCTRL
T
(1)
(1)
BCCKO_O
O
Description
GND
GND
GND
V
V
V
V
DD
DD
DD
DD
I
IGNORE1
CE1
S1
I1
I0
S0
CE0
IGNORE0
Global Clocking Resources
ug190_1_03_032206
Figure
ug190_1_04_032206
Figure 1-3
1-4.
0 (default), 1
FALSE (default),
TRUE
FALSE (default),
TRUE
Possible Values
O
illustrates
31

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