XC3S500E-4CPG132C Xilinx Inc, XC3S500E-4CPG132C Datasheet - Page 131

• Manufacturer Part Number: XC3S500E-4CPG132C
• Description: FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 132-Pin CSBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S500E-4CPG132C

• Package: 132CSBGA
• Family Name: Spartan®-3E
• Device Logic Cells: 10476
• Device Logic Units: 1164
• Device System Gates: 500000
• Number Of Registers: 9312
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 92
• Ram Bits: 368640
• Number Of Logic Elements/cells: 10476
• Number Of Labs/clbs: 1164
• Total Ram Bits: 368640
• Number Of I /o: 92
• Number Of Gates: 500000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 132-TFBGA, CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1536 - KIT STARTER SPARTAN-3E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1484

Table 92: Timing for the IOB Output Path
DS312-3 (v3.8) August 26, 2009
Product Specification
Notes:
1.
2.
3.
Clock-to-Output Times
T
Propagation Times
T
T
Set/Reset Times
T
T
IOCKP
IOOP
IOOLP
IOSRP
IOGSRQ
Symbol
The numbers in this table are tested using the methodology presented in
Table 77
This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the
data Output. When this is true, add the appropriate Output adjustment from
For minimum delays use the values reported by the Timing Analyzer.
R
and
Table
When reading from the Output Flip-Flop
(OFF), the time from the active transition
at the OCLK input to data appearing at
the Output pin
The time it takes for data to travel from
the IOB’s O input to the Output pin
The time it takes for data to travel from
the O input through the OFF latch to the
Output pin
Time from asserting the OFF’s SR input
to setting/resetting data at the Output
pin
Time from asserting the Global Set
Reset (GSR) input on the
STARTUP_SPARTAN3E primitive to
setting/resetting data at the Output pin
80.
Description
www.xilinx.com
LVCMOS25
output drive, Fast slew
rate
LVCMOS25
output drive, Fast slew
rate
LVCMOS25
output drive, Fast slew
rate
Conditions
Table 95
Table
(2)
(2)
(2)
94.
, 12 mA
, 12 mA
, 12 mA
and are based on the operating conditions set forth in
DC and Switching Characteristics
Device
All
All
All
Speed Grade
Max
2.18
2.24
2.32
3.27
8.40
-5
Max
2.50
2.58
2.67
3.76
9.65
-4
Units
ns
ns
ns
ns
ns
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