5962-9071506MUA QP SEMICONDUCTOR, 5962-9071506MUA Datasheet - Page 21

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5962-9071506MUA

Manufacturer Part Number
5962-9071506MUA
Description
Manufacturer
QP SEMICONDUCTOR
Datasheet

Specifications of 5962-9071506MUA

Lead Free Status / RoHS Status
Not Compliant

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Part Number:
5962-9071506MUA
Quantity:
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DSCC FORM 2234
APR 97
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for
device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed
for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections
(see 4.4.1 through 4.4.4).
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
4.4.1 Group A inspection.
d.
a.
b.
c.
a. Tests shall be as specified in table IIA herein.
b. Subgroups 5 and 6 of table I of method 5005 of MIL-STD-883 shall be omitted.
c.
e. Subgroup 4 (C
DEFENSE SUPPLY CENTER COLUMBUS
O/V (latch-up) tests shall be measured only for initial qualification and after any design or process changes which may
affect the performance of the device. For device class M, procedures and circuits shall be maintained under document
revision level control by the manufacturer and shall be made available to the preparing activity or acquiring activity upon
request. For device classes Q and V, the procedures and circuits shall be under the control of the device
manufacturer's TRB in accordance with MIL-PRF-38535 and shall be made available to the preparing activity or
acquiring activity upon request. Testing shall be on all pins, on five devices with zero failures. Latch-up test shall be
considered destructive. Information contained in JEDEC Standard EIA/JESD 78 may be used for reference.
design changes which may affect input or output capacitance. Capacitance shall be measured between the designated
terminal and GND at a frequency of 1 MHz. Sample size is 15 devices with no failures, and all input and output
terminals tested.
Test condition C or D. The test circuit shall be maintained by the manufacturer under document revision level control
and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs,
outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-
STD-883.
T
Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table. For device classes Q and V,
subgroups 7 and 8 shall include verifying the functionality of the device.
A
= +125°C, minimum.
MICROCIRCUIT DRAWING
COLUMBUS, OHIO 43218-3990
STANDARD
IN
and C
OUT
measurements) shall be measured only for initial qualification and after any process or
SIZE
A
REVISION LEVEL
B
SHEET
5962-90715
21

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