FDC37C665GT-MS Standard Microsystems (SMSC), FDC37C665GT-MS Datasheet - Page 33

• Manufacturer Part Number: FDC37C665GT-MS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C665GT-MS

• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

DATA RATE SELECT REGISTER (DSR)
Address 3F4 WRITE ONLY
This register is write only. It is used to program
the data rate, amount of write precompensation,
power down status, and software reset.
data
Configuration Control Register (CCR) not the
DSR, for PC/AT and PS/2 Model 30 and
BIT 0 and 1 DATA RATE SELECT
These bits control the data rate of the floppy
controller.
corresponding to the individual data rates. The
data rate select bits are unaffected by a
software reset, and are set to 250kb/s after a
hardware reset.
BIT 2 through 4
SELECT
These three bits select the value of write
precompensation that will be applied to the
WDATA output signal.
precompensation values for the combination of
these bits settings.
starting track number to start precompensation.
the configure command.
BIT 5 UNDEFINED
Should be written as a logic "0".
BIT 6 LOW POWER
A logic "1" written to this bit will put the floppy
controller into Manual Low Power mode. The
this starting track number can be changed by
rate
RESET
COND.
See Table 13 for the settings
is
RESET
S/W
programmed
7
0
Track 0 is the default
PRECOMPENSATION
Table 12 shows the
POWER
DOWN
6
0
using
5
0
0
The
the
COMP2
PRE-
33
4
0
Microchannel applications.
can set the data rate in the DSR. The data rate
of the floppy controller is the most recent write
of either the DSR or CCR.
unaffected by a software reset.
reset
corresponds to the default precompensation
setting and 250kb/s.
floppy controller clock and data separator
circuits will be turned off.
come out of manual low power mode after a
software reset or access to the Data Register or
Main Status Register.
BIT 7 SOFTWARE RESET
This active high bit has the same function as the
DOR RESET (DOR bit 2) except that this bit is
self clearing.
PRECOMP
COMP1
PRE-
Table 12 - Precompensation Delays
432
111
001
010
011
100
101
110
000
3
0
will
set
COMP0
PRE-
2
0
the
PRECOMPENSATION
Default (See Table 14)
0.00 ns-DISABLED
DSR
DRATE
SEL1
125.00 ns
166.67 ns
208.33 ns
250.00 ns
41.67 ns
83.34 ns
DELAY
1
1
Other applications
The controller will
to
DRATE
SEL0
The DSR is
02H,
A hardware
0
0
which