CY7C341-25RC Cypress Semiconductor Corp, CY7C341-25RC Datasheet - Page 6

• Manufacturer Part Number: CY7C341-25RC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C341-25RC

• Family Name: MAX®
• # Macrocells: 192
• Number Of Usable Gates: 3750
• Frequency (max): 62.5MHz
• Propagation Delay Time: 25ns
• Number Of Logic Blocks/elements: 12
• # I/os (max): 64
• Operating Supply Voltage (typ): 5V
• In System Programmable: No
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 84
• Package Type: Windowed PGA
• Memory Type: EPROM
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-03034 Rev. *B
External Synchronous Switching Characteristics Over the Operating Range
t
t
t
t
t
t
t
t
t
t
t
f
f
f
f
t
Notes:
13. This specification is a measure of the delay associated with the internal register feedback path. This is the delay from synchronous clock to LAB logic array
14. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which a state machine configuration with external feedback can
15. This specification indicates the guaranteed maximum frequency at which a state machine, with internal-only feedback, can operate. If register output states
16. This frequency indicates the maximum frequency at which the device may operate in data path mode (dedicated input pin to output pin). This assumes data
17. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which an individual output or buried register can be cycle by a clock
18. This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin.
H
WH
WL
RW
RO
RR
PW
PR
PO
CF
P
MAX1
MAX2
MAX3
MAX4
OH
Parameter
input. This delay plus the register set-up time, t
the same LAB. This parameter is tested periodically by sampling production material.
operate. It is assumed that all data inputs and feedback signals are applied to dedicated inputs. All feedback is assumed to be local originating within the same
LAB.
must also control external points, this frequency can still be observed as long as this frequency is less than 1/t
input signals are applied to dedicated input pins and no expander logic is used. If any of the data inputs are I/O pins, t
signal applied to the dedicated clock input pin.
Input Hold Time from
Synchronous Clock Input
Synchronous Clock Input
High Time
Synchronous Clock Input
Low Time
Asynchronous Clear Width
Asynchronous Clear to
Registered Output Delay
Asynchronous Clear Recovery
Asynchronous Preset Width
Asynchronous Preset Recovery
Time
Asynchronous Preset to
Registered Output Delay
Synchronous Clock to Local
Feedback Input
External Synchronous Clock Period
(1/f
External Feedback Maximum
Frequency (1/(t
Internal Local Feedback Maximum
Frequency, lesser of (1/(t
or (1/t
Data Path Maximum Frequency, least
of 1/(t
or (1/t
Maximum Register Toggle
Frequency
(1/(t
Output Data Stable Time from
Synchronous Clock Input
MAX3
WL
[3, 6]
CO1
WL
CO1
+ t
)
[3]
)
+ t
[3, 16]
WH
)
[3, 15]
WH
))
[3, 17]
), 1/(t
CO1
[3, 13]
Description
S1
+ t
+ t
S1
S1
H
))
USE ULTRA37000™ FOR
, is the minimum internal period for an internal synchronous state machine configuration. This delay is for feedback within
),
[5]
[6]
S1
[3, 14]
[6]
[3, 18]
[3, 6]
[3, 6]
+ t
ALL NEW DESIGNS
CF
[3, 7]
))
Com’l
Mil
Com’l
Mil
Com’l
Mil
Com’l
Mil
Com’l
Mil
Com’l
Mil
Com’l
Mil
Com’l
Mil
Com’l
Mil
Com’l
Mil
Com’l
Mil
Com’l
Mil
Com’l
Mil
Com’l
Mil
Com’l
Mil
Com’l
Mil
Min.
34.5
34.5
55.5
55.5
62.5
62.5
62.5
62.5
25
25
25
25
25
25
25
25
16
16
0
0
8
8
8
8
3
3
7C341-25
Max
25
25
25
25
[6]
3
3
(continued)
Min.
27.7
27.7
10
10
10
10
30
30
30
30
30
30
30
30
20
20
43
43
50
50
50
50
7C341-30
0
0
3
3
CO1
.
Max
30
30
30
30
S2
3
3
is the appropriate t
Min.
12.5
12.5
12.5
12.5
22.2
22.2
40.0
40.0
40.0
40.0
35
35
35
35
35
35
35
35
25
25
33
33
7C341-35
0
0
3
3
CY7C341
S
for calculation.
Max
35
35
35
35
5
5
Page 6 of 15
Unit
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns