MPCBL0050N02Q Intel, MPCBL0050N02Q Datasheet
MPCBL0050N02Q
Specifications of MPCBL0050N02Q
MPCBL0050N02Q Summary of contents
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... Intel NetStructure Single Board Computer Technical Product Specification September 2007 ® MPCBL0050 Order Number: 318146-001 ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. ...
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... September 2007 Order Number: 318146-001 Rear Transition Module........................................................ 19 2.2.1.1 Intel NetStructure® MPRTM0040 ............................ 19 2.2.1.2 Intel NetStructure® MPRTM0050 ............................ 20 Dual-Core Intel® Xeon® 5138 LV 2.13GHz Processor ............. 21 Chipset ............................................................................. 21 ® 2.2.3.1 Intel 5000 Memory Controller Hub ........................ 21 ® 2.2.3.2 Intel 6321ESB I/O Controller Hub ......................... 22 ® ...
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... Field Replaceable Unit (FRU) Information ........................................ 103 5.4.1 5.4.2 5.4.3 5.4.4 ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 4 Zone 3 Rear Transition Module Power Connector (J30) .............54 Zone 3 Rear Transition Module Data/Control Connector (J31)....55 Zone 3 Rear Transition Module Data Connector (J32)...............56 Zone 3 Rear Transition Module Data/Control Connector (J33) ...
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... Order Number: 318146-001 MPCBL0050 FRU Record .................................................... 106 FRU Area for Customer-Specific Information......................... 116 Writing to the Customer FRU MRA....................................... 116 Functional Description ....................................................... 119 Update Modes .................................................................. 119 Password Clear DIP Switch ................................................ 143 Intel NetStructure 141 147 ® MPCBL0050 Single Board Computer Technical Product Specification 5 ...
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... Setting up a Serial Over LAN Session.............................................. 170 9.8.1 9.8.2 ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 6 Processor Submenu........................................................... 149 Memory Submenu............................................................. 149 ATA Controller Submenu .................................................... 150 Mass Storage Submenu ..................................................... 150 Serial Port Submenu ......................................................... 150 USB Configuration Submenu ...
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... Remove Existing Packages................................................. 188 10.4.3 Installing the sbcutils Package............................................ 189 10.5 System Configuration................................................................... 189 10.5.1 Introduction..................................................................... 189 10.5.2 Configuring the Intel NetStructure 10.6 SBC Update Utility ...................................................................... 192 10.6.1 Communication Interfaces ................................................. 192 10.6.2 IPMC Operational Code Firmware Update Modes ................... 194 10.6.3 Staged Update Process...................................................... 195 10 ...
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... Customer Support 16.1 Customer Support........................................................................ 250 16.2 Technical Support and Return for Service Assistance......................... 250 ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 8 10.6.15.1SDR Update via KCS ............................................ 212 10.6.15.2RTM SDR Update via KCS ..................................... 212 10.6.15.3SDR Update via RMCP Bridge ................................ 213 ...
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... Query device ..................................................................................... 186 45 Changing CPU crystal frequency ........................................................... 187 46 KCS - local communication from CPU to local IPMC ................................. 193 47 KCS bridge - local communication from CPU to local IPMC bridged to RTM . 193 September 2007 Order Number: 318146-001 ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 9 ...
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... System reset sources and actions ......................................................... 122 42 IPMC reset sources and actions ............................................................ 124 43 CMM commands for FRU control options ................................................ 126 44 Returned values from the Get Message command ................................... 127 ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 10 MPCBL0050— September 2007 Order Number: 318146-001 ...
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... Staged update process........................................................................ 195 76 Common command line options and arguments...................................... 198 77 Informational messages ...................................................................... 219 78 Warning and error messages ............................................................... 222 79 Mapping of physical slot to IPMB address in Intel NetStructure 14U Shelf.......................................................................................... 232 80 Board components ............................................................................. 234 81 Environmental specifications ................................................................ 234 82 Reliability estimate data ...................................................................... 235 83 Operating voltage ranges .................................................................... 236 84 Total measured powe ...
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... Revision History Date Revision September 2007 001 Initial release of this document. ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 12 Description Order Number: 318146-001 MPCBL0050— September 2007 ...
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... Introduction 1.1 Document Organization This document gives technical specifications related to the Intel NetStructure MPCBL0050 Single Board Computer (SBC). The MPCBL0050 is designed in accordance with the standards of the Advanced Telecommunications Compute Architecture (AdvancedTCA*) Design Guide for high availability, switched network computing. This document is intended for support during system product development and while sustaining a product ...
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... Allows a single (or dual) physical processor, to appear as two (or quad) logical processors Technology-aware operating system. Inter-Integrated Circuit. A two-wire interface commonly used to carry management data. Intel® Boot Agent. Software that allows your networked client computer to boot using a program code image supplied by a remote server. I/O Controller Hub MPCBL0050— ...
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... September 2007 Order Number: 318146-001 Definition Integrated Device Electronics. A common, low-cost disk interface. Intelligent Platform Management Bus. A physical two-wire medium to carry IPMI information. Intelligent Platform Management Controller. A microcontroller on the baseboard responsible for low-level system management. Also referred to as BMC. Intelligent Platform Management Interface. A programming model for system management ...
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... Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 16 MPCBL0050—Introduction September 2007 Order Number: 318146-001 ...
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... SAS links to the RTM and AdvancedMC slot (See 2.2.6, “AdvancedMC Slot” The SBC incorporates an Intelligent Platform Management Controller (IPMC) that monitors critical hardware functionality of the board such as temperature and voltage, responds to commands from the shelf manager, and reports events. ...
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... PCI-Ex Update Channel Hub x8 PCI-Ex x4 PCI-Ex x4 PCI-Ex Memory 4 x FBDIMM channel Front Side Bus 1066MT/s Four FBDIMM Sockets Dual-Core Intel® Xeon® 5138 DDR2-533 processor LV 2.13GHz Redundant IPMB September 2007 Order Number: 318146-001 MPCBL0050—Feature Overview J30 J30 J31-33 X3 SAS ...
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... Intel NetStructure® MPRTM0040 • Intel NetStructure® MPRTM0050 2.2.1.1 Intel NetStructure® MPRTM0040 The Intel NetStructure® MPRTM0040 Rear Transition Module (RTM) supports the following interfaces: • One USB port • One Serial console interface • Four Serial Attached SCSI (SAS) ports for remote storage connectivity • ...
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... Intel NetStructure® MPRTM0050 The Intel NetStructure® MPRTM0050 Rear Transition Module (RTM) supports the following interfaces: • One USB port • One Serial console interface • Four Serial Attached SCSI (SAS) ports for remote storage connectivity • One on-board SAS hard drive (SAS HDD not included) • ...
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... I/O Controller (ICH) ® • Intel 82571EB Gigabit Ethernet Controller Although a brief overview is provided in this document, detailed component information can be found in the documentation for the respective devices. Please refer to the Intel web page: http://www.intel.com ® 2.2.3.1 Intel 5000 Memory Controller Hub ...
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... The MCH is a root class component as defined in the PCI Express Interface Specification, Rev1.0a. The MCH interfaces with the Intel® 6321ESB ICH via a dedicated Enterprise South Bridge Interface (ESI) port together with x8 PCI Express port, providing appropriate bandwidth for I/O interfaces connected to to the ICH. ...
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... FB DIMM FB DIMM Connector Connector 22.5 Deg SMT 22.5 Deg SMT DIMM2 DIMM 3 CHANNEL 1 CHANNEL 2 BRANCH 1 Memory Controller Intel NetStructure FB-DIMM (up to 4GB) FB DIMM Connector 22.5 Deg SMT 14 10 DIMM 4 CHANNEL 3 ® MPCBL0050 Single Board Computer Technical Product Specification 23 ...
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... The MPCBL0050 SBC implements six Gigabit Ethernet (GbE) interfaces. Two of these are supported by Intel interface on the AdvancedTCA backplane to support PICMG* 3.0 (base). The remaining four are supported with two Intel routed to the fabric interface on the AdvancedTCA backplane to support the 3.1 option 2 (fabric) specifications. ...
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... All four ports directed to the RTM RJ45 for rear connectivity. AMC GbE ports connected to the backplane. For details on available redirection options, please refer to BIOS setup section. September 2007 Order Number: 318146-001 CPU CPU Intel® 5000P x8 PCI-Ex MCH GbE GbE 82571EB 82571EB Mux ...
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... Four GbE ports directed to the backplane (PICMG 3.1 Option 2) Advanced MC RJ45 RJ45 Figure 7. Two GbE ports directed to backplane, two GbE ports to front panel Advanced MC RJ45 RJ45 1000Base-T ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 26 CPU CPU Intel® 5000P x8 PCI-Ex MCH GbE GbE 82571EB 82571EB ...
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... The MPCBL0050 has a 4-port Serial Attached SCSI (SAS) controller that provides ports for AdvancedMC and RTM equipped with SAS HDD. The LSI1064 SAS controller is connected to the PCI-X bus of the Intel have a serial point-to-point interface using a differential transmit/receive pair. The SAS controller has a flash device that is used to store its firmware. ...
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... Serial Ports The MPCBL0050 supports one serial port connected to the Intel Controller Hub. The serial port is routed to the front panel RJ-45 connector and the RTM RJ-45 connector. Since they are connected together, only one port can be used at a time (front panel or RTM). ...
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... Note: Although the AdvancedMC connector provides access to an SAS port, Intel has not validated AdvancedMC cards supporting an SAS HDD. Due to thermal constraints, using such a card may not be possible in certain environments. Caution: Never ship the MPCBL0050 SBC with any AdvancedMC modules installed. ...
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... FWH1 also stores its own configuration which is independent of the FWH0 settings. 2.2.7.3 EFI Backup Mechanism The on-board Intelligent Platform Management Controller (IPMC) manages which of the two BIOS flash devices is selected during the boot process. The IPMC can change the BIOS flash device selection from FWH0 to FWH1 and reset the processor. ...
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... VOLT REG HOLD-UP CAPACITOR LM5035 VOLT REG 35V – 80V LM5035 VOLT REG Free run LM5035 VOLT REG LM5035 VOLT REG Intel NetStructure 1,5V ICH + MCH ref FB-DIMM 1,8V 1,8V VOLT REG 3,3V 3,3V domain BMC I/O all devices ref BASE I/F ...
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... During normal board operation IPMC’s responsibility to monitor onboard temperature and inform the Shelf Manager by logging SEL events. Autonomous power- down is last-resort protection intended to save the board in the event of IPMC or Shelf Manager failure. ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 32 MPCBL0050—Feature Overview ...
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... Feature Overview—MPCBL0050 2.2.10 Intelligent Platform Management Controller The MPCBL0050 uses the Renesas* HD64F2166 processor, as the Intelligent Platform Management Controller (IPMC). The IPMC is a management subsystem providing monitoring, event logging, and recovery control. The IPMC serves as the gateway for management applications to access the platform hardware. Some of the key features are: • ...
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... Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 34 MPCBL0050—Feature Overview September 2007 Order Number: 318146-001 ...
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... Front Panel Connectors Figure 10. Front panel connectors Recessed Reset Switch September 2007 Order Number: 318146-001 RJ45 GbE Fabric Interface port RJ45 GbE Fabric Interface port RJ45 Serial Port Connector USB Connector Intel NetStructure AdvancedMC slot ® MPCBL0050 Single Board Computer Technical Product Specification 35 ...
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... A single serial port interface is provided on the front edge of the card using an RJ-45 style shielded connector. The connector is an 8-pin RJ-45. connector and Table 7 translation. Figure 12. Serial port connector (J4) ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 36 Figure 11 Pin 1 gives the pin assignments. Figure 13 MPCBL0050— ...
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... Two Ethernet ports are provided on the front edge of the board using an RJ-45 style shielded connector (Bel Fuse* L829-1BIT-43). Table 8 gives the pin assignments. September 2007 Order Number: 318146-001 Male RJ- Connector Pin Pin Female DB-9 Connector 9 6 Figure 14 shows the connector and ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 37 ...
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... The reset button is available at the front panel as shown in 3.2 Front Panel LEDs Figure 15 shows LEDs the MPCBL0050 SBC uses to indicate status. ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 38 Comments Bi-directional lane 1, positive polarity Bi-directional lane 1, negative polarity ...
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... RED: The board is out of service. OFF: The board is running possible for a user to override the default IPMC behavior of the LED using AdvancedTCA FRU LED Control commands. Possible States: OFF / RED / AMBER Intel NetStructure FI port Link LED FI port Activity LED FI port Link LED FI port Activity LED Table 9 ...
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... Link/Activity Ports E & F Link Speed Ports E & F Activity SAS Ports Activity ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 40 Function Function: Health (AdvancedTCA LED 2). The SBC health is based on an aggregation of IPMI sensors, like board temperature and voltage. GREEN: The SBC is healthy. ...
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... Figure 16. Backplane and on-board connector/DIP switch locations September 2007 Order Number: 318146-001 SW3 J2 SW2 SW1 Intel NetStructure Table 10 U31 U30 J30 J31 J32 J33 J20 J23 P10 U28 U29 ® ...
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... Note: The DIP switch descriptions presented below only to the production version of the MPCBL0050 (only 3 DIP switch modules on the board: SW1, SW2, SW3). For details on preproduction boards, please contact your Intel representative. Table 11. DIP switch SW1 ...
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... RESERVED RESERVED On = Enable IPMC serial port (required for IPMC boot block upgrade Payload power on with IPMC in reset mode (Allows starting board without IPMC) RESERVED RESERVED ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification Off Off Off Off Off Off ...
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... GA2 - N.C. B27 PWR4 - 12V_AMC1 B28 GND9 - GND B29 Rx2+ - SAS_RX3_P B30 Rx2- - SAS_RX3_N B31 GND10 - GND ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 44 MPCBL0050—Connectors and LEDs Table 14. Comments Logic Ground AMC main power Presence 1 3.3V management power Geo Address - Bit 0 < ...
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... AMC Port PCI-Ex from MCH port 6 Lane 2 | Logic Ground AMC Port PCI-Ex to MCH Port 6 Lane 3 | Logic Ground AMC Port PCI-Ex from MCH port 6 Lane 3 | Logic Ground IPMB-L Data 12V AMC main power ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 45 ...
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... Rx11+ - MCH_EXP7RXP<3> B110 GND37 - GND B111 Tx12- - AMC_12_TXN_B1 B112 Tx12+ - AMC_12_TXP_B1 B113 GND38 - GND B114 Rx12- - AMC_12_RXN_B1 ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 46 MPCBL0050—Connectors and LEDs Logic Ground Not Used | Logic Ground Not Used | Logic Ground ...
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... AMC Port AMC I/O connection from RTM | Logic Ground AMC Port AMC I/O connection to RTM | Logic Ground AMC Port AMC I/O connection from RTM | Logic Ground AMC Port AMC I/O connection to RTM ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 47 ...
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... Two ground pins • 12 unused (but physically present) pins Figure 18 shows the mechanical drawing of the connector. The pin assignments are listed in Table 15. ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 48 | Logic Ground AMC Port AMC I/O connection from RTM | ...
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... Alignment Feature September 2007 Order Number: 318146-001 IPMB and HA Interface Dual -48V DC Second Third Mate Mate Intel NetStructure First Mate Shelf Ground and Logic Ground First Mate -48V DC Returns First Mate -48V DC Precharge ® MPCBL0050 Single Board Computer Technical Product Specification ...
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... Zone 2 consists of two 120-pin HM-Zd connector, labeled J20 and J23, with 40 differential pairs. J20 provides Update Channel connectivity, while J23 provides base interface and fabric interface GbE ports connectivity. ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 50 MPCBL0050—Connectors and LEDs ...
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... Update Channel Port 1 - PCI-Ex form ESB2 - Lane 1 (TX1, RX1) Update Channel Port 2 - PCI-Ex form ESB2 - Lane 2 (TX2, RX2) Update Channel Port 3 - PCI-Ex form ESB2 - Lane 3 (TX3, RX3) The connector used is an AMP*/Tyco* part number 1469001-1 (Intel part number A66621-005). Figure 19 Figure 19 ...
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... The BG, DG, FG, and HG (G for Ground) columns contain the ground shields for the four columns of differential pairs. They have been omitted from the pinout tables below for simplification. All pins in the BG, DG, FG, and HG columns are connected to logic ground. ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 52 C ...
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... F[1]Tx1- BI_DB1- BI_DC1+ BI_DC1- (Rx1+) BI_DB1- BI_DC2+ BI_DC2- (Rx2-) No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect Intel NetStructure Terminated Terminated F[2]Rx1+ F[2]Rx1- Terminated Terminated F[1]Rx1+ F[1]Rx1- BI_DD1+ BI_DD1- BI_DD2+ BI_DD2- No Connect No Connect No Connect No Connect No Connect No Connect ...
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... A2(L) Shelf_GND Table 19. J30 signal descriptions (Sheet Pin Signal A1 Logic_GND A2 Shelf_GND B1 Logic_GND B2 +3.3V_MP C1 IPMI_Sclk C2 IPMI_Sdata ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 54 1 Table 18. Pin Signal E1(S) PS1# D1(S) 12V C1(M) IPMI_Sclk B1(L) Logic_GND A1(L) Logic_GND Comments Logic ground connection (long contact) ...
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... RTM is not installed. Test Mode State signal as defined in JTAG. Required on SBCs and RTMs with JTAG-enabled devices. Test Data Out signal as defined in JTAG. See TDI comments above. Output of RTM. Reserved. Intel NetStructure Reserved No Connect SA[1]RX+ ...
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... AP0[x] are signals routed from AdvancedMC to the RTM. • AMC_Port 20 is mapped to AP0[0] • AMC_Port19 to AP0[1] • AMC_Port18 to AP0[2] • AMC_Port17 to AP0[3] ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 56 Comments Serial Attached SCSI signals for transmit and receive portions of differential pairs ...
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... Eth3_Act 00 No Connect No Connect No Connect No Connect Reserved Reserved Comments GbE port E redirected from front board. GbE port F redirected from front board. LEDs for GbE port E LEDs for GbE port F Intel NetStructure Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect ...
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... Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 58 MPCBL0050—Connectors and LEDs September 2007 Order Number: 318146-001 ...
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... Removing the SBC before the Hot Swap LED is solid blue can lead to device corruption or failure. September 2007 Order Number: 318146-001 Section for detailed information on the function and operation of the Hot Intel NetStructure 3.4. ® MPCBL0050 Single Board Computer Technical Product Specification 59 ...
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... Do not operate the MPCBL0050 without filler panels or AdvancedMC modules installed. AdvancedMC module slots should not be left open or uncovered when the MPCBL0050 is in use. Figure 22. AdvancedMC filler panel ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 60 MPCBL0050—Operating the Unit 5441-01 ...
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... Before reattaching the top cover, ensure that the DIMM ejector latches are closed. If they are left open, installing of the top cover will not be possible. latches left in the closed (correct) position. September 2007 Order Number: 318146-001 Figure Table 4. Figure 24 ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 23. shows the 61 ...
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... Refer to the MPCBL0050 Compatibility Report for a list of devices validated. 4.7 Digital Ground to Chassis Ground Connectivity By default, the board is shipped with the digital ground connected to the chassis ground by a metal standoff. ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 62 Section 4.2. ...
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... The removed standoff would only be needed again to reverse the current procedure (to once again connect the digital ground to the chassis ground). September 2007 Order Number: 318146-001 Section 4.5 for details on cover removal). Figure ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 25. 63 ...
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... Booting from a PATA Flash (On-board) Two Parallel ATA flashes are available on the board. Each of them can be used for booting operating system. ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 64 for a complete description of the EFI options. Section 3.1.2 for detailed information on selecting boot devices ...
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... ICH Base Interface; Port 0, Channel 1, ICH Base Interface; Port 0, Channel 2 Fabric Interface; Port 0, Channel 1 (Ports C and D can be jointly selected to MCH Port 4 connect to the backplane or to the RJ45 connectors on the RTM (optional) Intel NetStructure ® MPCBL0050 Single Board Computer Technical Product Specification 65 ...
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... In the IPMI specification (23.2), parameter #5 (MAC address) of the Get LAN Configuration Parameters Command will be populated automatically with the base interface MAC address. Alternatively, using ipmitool from the payload processor, the command is: “ipmitool lan print 1” ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 66 MPCBL0050—Operating the Unit PCI Express Port PICMG 3 ...
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... Intra-building (same building) only: Shielded Ethernet cable SFTP5e. Intra-building wiring (cabling) only, directly connects equipment within the same frame, cabinet or line-up and where equipment is separated by a distance less. Shielded Category 5e cable with DB-9 to RJ45 converter. External USB shielded cable Intel NetStructure Max Length 100m 6m 5m ® ...
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... Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 68 MPCBL0050—Operating the Unit September 2007 Order Number: 318146-001 ...
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... Hardware Management—MPCBL0050 5.0 Hardware Management The Intelligent Platform Management Controller (IPMC) is based on the Renesas* microcontroller, model HD64F2166. This controller is a 16-bit processor with 40 KBytes of internal RAM and 512 kBytes of internal flash. It supports up to six I (master/slave), three serial-ports, a low-pin count (LPC) interface, and an A/D and DAC. This microcontroller is also capable of addressing MBytes and has external access to 2 MBytes of flash memory ...
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... KCS interface for POST error logging purposes, fault resilient purposes and critical interrupts. ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 70 27. CPU MCH ICH Intelligent Platform Management Controller (IPMC) IPMB B Internal Flash IPMB A External SRAM Serial Temp 256KB ...
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... FPGA and ICH is used to monitor the Port 80 codes during power up. In the event of a board failing to power up, a user can query the last five Port 80 codes stored in the FPGA registers using an Intel OEM IPMI command. To increase the reliability of the MPCBL0050 SBC, a watchdog timer is implemented. ...
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... See the Intelligent Platform Management Interface Specification, Version 2.0 and Intelligent Platform Management Interface Specification, Version 2.0 for sensor and event/reading-type table information. The following sections ...
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... SEL event is generated. Some sensors generate events asynchronously and do not need to be polled. Typically, only analog sensors require polling. Managing Device The managing device is the hardware device that a sensor is connected to. September 2007 Order Number: 318146-001 Table 28 to describe a ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 73 ...
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... Progress 0Fh 6Fh 04h Critical 05h Sensor Interrupt Critical Int 07h Specific 07h 6Fh 13h 08h ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 74 Event Data Event Offset ED1 Byte Byte [3: Power Off Power Cycle Power Fault Power Fault ...
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... Sel Full 05h FFh FFh Sel Almost Full (95%) 00h Session Activation FFh FFh As per IPMI As per IPMI Spec. Spec. 01h Session Deactivation Technical Product Specification 75 Assert Readab / De- le Event assert Value / Events Offsets N N N/A ® Intel NetStructure MPCBL0050 Single Board Computer ...
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... Version Sensor Change Specific Version Change 0Eh 2Bh 6Fh 04h 05h 06h 07h ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 76 Event Data Event Offset ED1 Byte Byte [3: Hardware change detected FFh FFh with associated Entity. ...
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... C D [u,l][ nr,c,nc – – [u,l][ nr,c,nc] Technical Product Specification 77 Assert Readab / De- le Event assert Value / Events Offsets N/A As & De Analog A – & De Analog A – & De Analog A – & De Analog A – & De Analog ® Intel NetStructure MPCBL0050 Single Board Computer ...
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... Voltage Threshold 1.2V Early PHY 25h R, T 02h 01h 1.1V FIC Voltage Threshold 27h R, T 02h 01h (Fabric) ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 78 Event Data Event Offset ED1 Byte Byte [3: – – [u,l][ nr,c,nc] – ...
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... Value / Events Offsets As & De Analog A – & De Analog A – & De Analog A – & De Analog A X 0.5 As & De Analog A X 0.5 As & De Analog A X 0.5 As & De Analog & De Analog A X 0.5 As & De Analog & De Analog ® Intel NetStructure MPCBL0050 Single Board Computer ...
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... Digital EFI BIOS FWH0 OEM 54h Discrete Flash C0h 03h 01h ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 80 Event Data Event Offset ED1 Byte Byte [3: Fault Status Asserted Asserted on one of the two: -EFI BIOS detects an ...
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... PEF. Agent Not Responding. Graceful shutdown request 05h to agent via IPMC did not occur due to missing or malfunctioning local agent. Technical Product Specification 81 Assert Readab / De- le Event assert Value / Events Offsets - Yes N/A A ® Intel NetStructure MPCBL0050 Single Board Computer ...
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... System Sensor 04h System Event 83h Event Specific 12h 6Fh 05h 00h Sensor Button Button 84h Specific 14h 6Fh 02h ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 82 Event Data Event Offset ED1 Byte Byte [3: Legacy On Legacy Off FFh ...
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... IPMC asserts CPU NMI signal. This is event-only sensor. 00h State Deasserted FFh FFh 01h State Asserted Technical Product Specification 83 Assert Readab / De- le Event assert Value / Events Offsets As &De – N N N/A As & De – A – N/A ® Intel NetStructure MPCBL0050 Single Board Computer ...
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... PICMG Hot Sensor SBC FRU Hot 8Ah Swap Event Specific Swap F0h 6Fh 04h 05h 06h 07h ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 84 Event Data Event Offset ED1 Byte Byte [3: Last IPMC reset caused by internal watchdog circuit, ...
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... FFh FFh 04h M4 - FRU active M5 – FRU deactivation 05h request M6 - FRU deactivation in 06h Progress 07h M7 - Communication lost Technical Product Specification 85 Assert Readab / De- le Event assert Value / Events Offsets As – N/A As – N/A ® Intel NetStructure MPCBL0050 Single Board Computer ...
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... Sensor CPU 1 Processor 90h Specific 04h Status 07h 6Fh 05h 07h 08h 0Ah ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 86 Event Data Event Offset ED1 Byte Byte [3: IPMB A & B disabled IPBM A enabled IPMB B disabled FFh ...
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... CPU 1 Voltage Threshold 94h R, T Vcc 02h 01h CPU 2 Voltage Threshold 95h R, T Vcc 02h 01h ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 87 Event Data Event Offset ED1 Byte Byte [3: IERR + Thermal Trip FRB1 FRB2 FFh ...
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... Temp THreshold FI2 Junc TEMP 9Dh R,T 01h 01h Temp THreshold CPU1 PCBT 9Eh R,T TEMP 01h 01h ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 88 Event Data Event Offset ED1 Byte Byte [3: – – Transitioned to OK Transitioned to Non-Critical ...
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... C0h C0h OEM OEM DIMM 4 Size B3h 00h C0h C0h Microcontroll Sensor er / Specific Coprocessor CPU 1 Type B8h 00h 6Fh 16h ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 89 Event Data Event Offset ED1 Byte Byte [3: [u,l][nr,c,nc [u,l][nr,c,nc] C ...
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... LAN Link D Sts E6h Specific 27h 6Fh 01h 00h Sensor LAN Link E Sts LAN E7h Specific 27h 6Fh 01h ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 90 Event Data Event Offset ED1 Byte Byte [3: Bits: CPU 1 Type CPU [7:4]=Model ...
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... Discrete Fuse PlusB Fail EDh C0h 04h 01h 00h Digital OEM Fuse MinusB Discrete EEh Fail C0h 04h 01h ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 91 Event Data Event Offset ED1 Byte Byte [3: Heartbeat Lost - - (Link Down) Heartbeat ...
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... Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 92 MPCBL0050—Hardware Management Sensor- specific Description Offset Asserted when system power is off, Deasserted when 00h power is on Asserted and then deasserted as a result of a Power Cycle request. 01h Power Cycle condition is the situation when power is turned off, then immediately turned on ...
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... After board insertion IPMC detects firmware hub selection change. BIOS FWH change caused by DIP-SWITCH. BIOS FWH change caused by IPMI command “Reset BIOS Flash Type”. BIOS FWH change caused by IPMI command “Set Control State”. BIOS FWH change caused by FRB action Intel NetStructure Table . ® MPCBL0050 Single Board Computer ...
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... A PEF table entry matching an event where the filter entry has the Diagnostic Interrupt action indicated. • Watchdog timer pre-timeout expiration with NMI/Diagnostic Interrupt pre-timeout action enabled. ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 94 MPCBL0050—Hardware Management September 2007 ...
Page 95
... Chassis command “Pulse Diagnostic Interrupt” IERR action. Used and logged when NMI has been generated in response to IERR. 04h Note: this requires configure IERR action as “NMI” September 2007 Order Number: 318146-001 Table 34. Intel NetStructure ® MPCBL0050 Single Board Computer Technical Product Specification 95 ...
Page 96
... The list of all IPMC generated SEL events can be found in columns with the titles “Event Offset” and “Event”. Management software (not provided by Intel) running on the host processor is responsible for ensuring that SEL storage has sufficient space for SEL logging. Events are normally forwarded to the shelf manager and logged to SEL on the board ...
Page 97
... Intel NetStructure MPCBL0050 Single Board Computer Upper 0.80 1.00 1.05 1.35 1.05 1.35 1.30 1.70 1.30 1.70 2.08 2.10 1.60 2.00 Technical Product Specification 97 ...
Page 98
... SAS PCBT TEMP SAS Controller CPU1 voltage DC/DC PCBT regulator TEMP temperature OUTLET PCBT Temperature TEMP sensor CENTER PCBT Temperature TEMP sensor ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 98 MPCBL0050—Hardware Management Thresholds Lower 17 12.00 11.00 11.00 18 3.40 2.95 3. ...
Page 99
... A0 45C 5.00 12.00 A1 40C -5.00 5.00 A2 40C -5.00 5.00 ® Intel NetStructure MPCBL0050 Single Board Computer Upper 55.00 70.00 85.00 55.00 70.00 85.00 -30.00 -10.00 -30.00 -10.00 1.00 1.60 1.00 1.60 70.00 85.00 100.00 70.00 85 ...
Page 100
... IERR# is usually accompanied by a SHUTDOWN transaction on the processor system bus. • FRB-1 - Built In Self Test (BIST) failed • FRB-2 - Board hang during EFI BIOS Post ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 100 DC/DC PCBT CPU1 JUNCT & ...
Page 101
... IPMC firmware over the KCS interface. IPMC also logs information events at board boot. These events provide information on memory configuration detected by BIOS. Note: For details on memory detection and correction functionality, please refer to Intel 5000P data sheet available at www.intel.com. 5.3.4.1 Correctable Errors MCH provides detection and correction of any DRAM device failure ...
Page 102
... IPMC firmware when the board goes through either cold or warm reset explicit IPMI command received by the IPMC via the available interfaces (IPMB or KCS). Please refer to Table Note: ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 102 for the POST codes list. ...
Page 103
... Inventory information on the MPCBL0050 is divided into different areas that are written to at manufacturing time. Some information may be written by the BIOS during initialization, which are identified where necessary. September 2007 Order Number: 318146-001 ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 103 ...
Page 104
... Base interface MAC address record • Board UUID record • General board info record with version info for BIOS, Firmware, CPU and RAM Information ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 104 MPCBL0050—Hardware Management September 2007 ...
Page 105
... Definition v1.0 Specification. MPCBL0050 SBC. Note that the table is an illustration. The actual structure that is implemented can be found using the FRU file itself. Table 36. Additional board-specific information Information Manufacturer ID (Intel IANA number) Record Version Type/Length No. of CPUs Type/Length RAM Information Type/Length ...
Page 106
... The “Common”, “Board”, and “Product” fields are used by Intel during manufacturing and are used to program all the relevant board information into the FRU. The “MULTIREC” Intel multi-record area allocated for use by the EFI BIOS to program the relevant version information to the FRU during power up. ...
Page 107
... Product Info Area Format Version Bit Fields // Product Info Area Length (in multiples of 8 bytes) // Language Code // Product Manufacturer Name // Product Name (full product code, for example // Product Part Number (TA# number, example: "D71156-001") // Product Version (not used) Intel NetStructure ® MPCBL0050 Single Board Computer Technical Product Specification 107 ...
Page 108
... Link Descriptor for Base Ethernet CH1 Link Descriptor for Base Ethernet CH2 Port 0 & Ethernet 1 Port Port Port 0 & Ethernet 2 Port 1 ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 108 // Product Serial Number // Asset Tag // FRU File ID - available for customization // Customer Defined Field 1 ' ...
Page 109
... As per PICMG3.0 // PICMG ID For Carrier Activation and Current Management // Record Format Version // Max Internal Current in 1/10 Amp Increments // Activation Readiness in Seconds // Module Descriptor Count // IPMB-L address of the AMC Bay Intel NetStructure ® MPCBL0050 Single Board Computer Technical Product Specification 109 ...
Page 110
... AMC P9 -> PCI Ex x8 (MCH 01// AMC P10 -> PCI Ex x8 (MCH 01// AMC P11 -> PCI Ex x8 (MCH 01// AMC P13 -> RTM 01// AMC P14 -> RTM P7 ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 110 // max current, in tenths of Amps at 12V, that can be routed // Field NOT USED ...
Page 111
... Record Checksum (zero checksum) // Header Checksum (zero checksum) // Manufacturer ID (PICMG per PICMG3.0 v. PICMG Record ID For Carrier Point-to-Point Connectivity // Record Format Version // Resource ID // Point to Point Port count // Record Type ID // Version Information Intel NetStructure ® MPCBL0050 Single Board Computer Technical Product Specification 111 ...
Page 112
... RTM Point-to-Point Interface Record for E-Keying 5A3100 00 ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 112 // Record Length // Record Checksum (zero checksum) // Header Checksum (zero checksum) // Manufacturer ID (PICMG per PICMG3.0 v. PICMG Record ID For AMC Point-to-Point Interface Record ...
Page 113
... RTM Channel 2 // RTM Channel 3 // RTM Channel 3 // Record Type Version Information // Record Length // Record Checksum (zero checksum) // Header Checksum (zero checksum) // Manufacturer ID // Record Version Intel NetStructure // GUID 2 (Tvl2) // GUID 3 (RSVD) // GUID 4 (RSVD) // GUID 5 (RSVD) ® MPCBL0050 Single Board Computer Technical Product Specification 113 ...
Page 114
... 570100 ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 114 // Record Type Version Information // Record Length // Record Checksum (zero checksum) // Header Checksum (zero checksum) // Manufacturer ID // Record Version // Record Type ID // Version Information // Record Length // Record Checksum (zero checksum) // Header Checksum (zero checksum) ...
Page 115
... FW Version (Major, Minor, Build BIOS Version BIOS Version End of Fields September 2007 Order Number: 318146-001 // Type/Length // FPGA Version Number // Type/Length // Board HW Version Number // Type/Length // BIOS FWH Selected 0/1 // Type/Length // Type/Length Intel NetStructure ® MPCBL0050 Single Board Computer Technical Product Specification 115 ...
Page 116
... FRU MRA records. The FRU structure for the MPCBL0050 SBC is defined by the FRU file. Users can utilize the standard IPMI command to write this data. There is room for customers to write data to the FRU after the Intel OEM-MRA records at the end of the FRU file. Note: The FRU area has a maximum size of 512bytes so additional MRA records added by the customer shall not exceed this limit ...
Page 117
... Gigabit Ethernet channels connected to the base interface and the four Gigabit Ethernet channels on the fabric interface. lists AdvancedMC link descriptors. September 2007 Order Number: 318146-001 CPU CPU Intel® 5000P x8 PCI-Ex MCH Mux GbE GbE 82571EB ...
Page 118
... The IPMC supports a maximum of 20 PEF entries. Initially, first 8 PEF table entries are reserved. Remaining entries (up to 20) are available for the user to configure. The only action available is to turn the Health LED to red. ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 118 ...
Page 119
... IPMC. The user will not have the ability to back up the “old” operational image. September 2007 Order Number: 318146-001 IPMC Boot Code Operational Code Intel NetStructure Flash Memory Partition A (Staged Upgrade Region) Flash Memory Partition B (Rollback Region) External Flash Memory ® ...
Page 120
... SBC, the Hot Swap LED remains lit, indicating it is safe to remove the SBC from the chassis. Warning: Removing the SBC prematurely can lead to corruption of files on the hard drive. ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 120 MPCBL0050—Hardware Management ...
Page 121
... When a soft reset request occurs, the BIOS determines whether to initiate a warm boot while leaving main memory intact or a cold boot that clears memory. summarizes hard and soft reset parameters. September 2007 Order Number: 318146-001 Meaning Table 40 ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 121 ...
Page 122
... Payload Reset Diagram Figure 31 illustrates the reset state of the payload with respect to the possible source of the reset request given in ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 122 Type The payload is reset via the SYSRESET* input signal of the I/O Controller Hub (ICH). This reset ...
Page 123
... The IPMI Chassis Control command is supported and can be used to generate a hard reset to the payload. The Intel OEM Set Processor State command, which is used by the EFI BIOS during POST, also generates a hard reset when used to disable a processor as part of the Fault Resilient Booting (FRB) algorithm. ...
Page 124
... Watchdog Timer Expiration The Watchdog Timer can be configured to cause a hard reset to the payload upon its expiration. Timeout and action can be configured in EFI BIOS. For more information, see the Intelligent Platform Management Interface Specification, Version 2.0. 5.12.6 FRB3 Failure Simultaneous with resetting the payload, the IPMC starts an internal FRB3 timer. If the EFI BIOS does not start the IPMI Watchdog Timer with the usage set for EFI BIOS/ FRB2, the IPMC resets the system when the internal FRB3 timer expires ...
Page 125
... IPMI BMC Cold Reset Command The IPMC firmware supports the ability to reset the IPMC via the IPMI Cold Reset command. For more information, see the Intelligent Platform Management Interface Specification, Version 2.0. 5.13.5 IPMC Operational Code Update with New FPGA Load IPMC firmware image file that is used for firmware upgrade always contains image of the FPGA ...
Page 126
... Specification. Through this command, the payload can be reset, rebooted, or have its diagnostics initiated. The FRU payload can be controlled by a command line via the CMM. The following Intel MPCMM0001/MPCMM0002 CMM commands are supported by the MPCBL0050. Equivalent commands from other shelf managers are available. Refer to the appropriate documentation for third party shelf managers ...
Page 127
... Byte Data 1 Completion Code 2 Channel September 2007 Order Number: 318146-001 Figure 33 will assist users that are developing their system Value Comments 00h 40h Administrator privilege, Channel 0 (IPMB 0) Intel NetStructure – – – ® MPCBL0050 Single Board Computer Technical Product Specification 127 ...
Page 128
... Table 46, “Intel OEM commands (net function 0x30h)” on page 130 • Table 47, “Intel OEM commands (Net Function 0x32h)” on page 139 • Table 48, “Intel OEM commands (net function 0x3Ah)” on page 140 ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification ...
Page 129
... Hardware Management—MPCBL0050 Table 45. Intel OEM commands (net function 0x06h) Net Function = Application (0x06), LUN = 00 Code Command Get Device 01h ID September 2007 Order Number: 318146-001 Request, Response Data Description Platform-specific response fields: Byte 2 (Device ID) – 0x20 Byte 3 (Device revision) – 0x01 Byte 4 (Firmware Revision 1) • ...
Page 130
... Table 46. Intel OEM commands (net function 0x30h) (Sheet Net Function = Intel Code Command Change EFI 01h BIOS boot Flash Set Control 05h State Get Control 06h State ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 130 ® General Application (0x30), LUN = 00 ...
Page 131
... Hardware Management—MPCBL0050 Table 46. Intel OEM commands (net function 0x30h) (Sheet Net Function = Intel Code Command Get Version 07h Data 0Ah- Reserved 0Fh 18h- Reserved 20h September 2007 Order Number: 318146-001 ® General Application (0x30), LUN = 00 Request, Response Data Request: Byte 1 – None Response: Byte 1 – ...
Page 132
... Table 46. Intel OEM commands (net function 0x30h) (Sheet Net Function = Intel Code Command Get DIMM 21h State Set DIMM 22h State ReArm 23h DIMMs 25h Reserved ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 132 ® General Application (0x30), LUN = 00 ...
Page 133
... Hardware Management—MPCBL0050 Table 46. Intel OEM commands (net function 0x30h) (Sheet Net Function = Intel Code Command Set 28h Processor State Get 29h Processor State ReArm 2Ah Processors Disable FRB3 2Bh Action September 2007 Order Number: 318146-001 ® General Application (0x30), LUN = 00 ...
Page 134
... Table 46. Intel OEM commands (net function 0x30h) (Sheet Net Function = Intel Code Command Get Serial 30h Port Capture Data Get Serial Port Capture 31h Configuratio n ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 134 ® General Application (0x30), LUN = 00 ...
Page 135
... Hardware Management—MPCBL0050 Table 46. Intel OEM commands (net function 0x30h) (Sheet Net Function = Intel Code Command Set Serial Port Capture 32h Configuratio n Set System 41h GUID 47h Reserved Internal Platform 48h Event Message Set SM 50h Signal September 2007 Order Number: 318146-001 ® ...
Page 136
... Table 46. Intel OEM commands (net function 0x30h) (Sheet Net Function = Intel Code Command Get SM 51h Signal Get Self Test 52h History Get IPMI 60h commands History ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 136 ® General Application (0x30), LUN = 00 ...
Page 137
... Hardware Management—MPCBL0050 Table 46. Intel OEM commands (net function 0x30h) (Sheet Net Function = Intel Code Command IPMI 61h commands history clear Graceful OS 70h Shutdown Get ACPI 82h Configuratio n Mode Set ACPI 83h Configuratio n Mode 86h thru Reserved 8Ch A0h thru Reserved ...
Page 138
... Table 46. Intel OEM commands (net function 0x30h) (Sheet Net Function = Intel Code Command Get NMI/ E6h INIT Source Set NMI/ EDh INIT Source NMI/INIT F7h Enable / Disable Get Latest FAh Port80 Codes ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 138 ® ...
Page 139
... Hardware Management—MPCBL0050 Table 47. Intel OEM commands (Net Function 0x32h) Net Function = Intel® Platform Specific (0x32), LUN = 00 Code Command 01h Get HW Info Get Power Unit 02h Status 55h Reserved 57h Reserved September 2007 Order Number: 318146-001 Request, Response Data Request: N/A Response: Byte 1 – ...
Page 140
... Table 48. Intel OEM commands (net function 0x3Ah) Net Function = Application (0x3A), LUN = 00 Code Command LAN Mux 26h Settings ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 140 Request, Response Data Description To set LAN configuration: Request: This commands allows changing the GbE ports Byte 1 -80h direction ...
Page 141
... The EFI BIOS implementation is based on the Intel® Platform Innovation Framework for EFI architecture and is compliant with all Intel Platform Innovation Framework for EFI architecture specifications specified in the Extensible Firmware Interface Reference Specification, Version 1.1. ...
Page 142
... If the user or administrator enters an incorrect password three times in a row during the boot sequence, the system is placed into a halt state. A system reset is required to exit out of the halt state. This feature makes it difficult to break the password by guessing at it. ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 142 Section 3 ...
Page 143
... EFI BIOS Boot Device Priority setup menu. September 2007 Order Number: 318146-001 Escape Sequence ESC 2 Enter EFI BIOS setup utility. ESC 4 Enter EFI BIOS setup utility. ESC 0 To save and exit EFI BIOS Setup Intel NetStructure Notes ® MPCBL0050 Single Board Computer Technical Product Specification 143 ...
Page 144
... EFI BIOS tries to boot the next boot device from the previous boot device that caused the IPMI watchdog timer to timeout. Figure 35 shows the boot sequence. ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 144 MPCBL0050—EFI BIOS Features for details ...
Page 145
... At this time, board starts to boot and concurrently starts the IPMI OS Load Watchdog TImer Success Fail Int19 can Success OS Boot Up OS clear IPMI watchdog timer Intel NetStructure Yes Start IPMI OS Load Watchdog Timer IPMI OS Load Watchdog Timeout? No ® MPCBL0050 Single Board Computer ...
Page 146
... The EFI BIOS supports PS/2 emulation of USB keyboards and mice. During POST, the EFI BIOS initializes and configures the root hub ports and then searches for a keyboard and/or a mouse on the USB hub and then enables them. ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 146 MPCBL0050— ...
Page 147
... By default EFI BIOS waits 10s for user input before continuing the boot procedure. To speed up the boot process, the user can change that value in the boot option menu. September 2007 Order Number: 318146-001 36. Intel NetStructure ® MPCBL0050 Single Board Computer Technical Product Specification 147 ...
Page 148
... Displays system memory size of recognized DIMMs Can set date Allows setting the current date Can set Time Specifies the current time Options Select to display Display CPU details, configure Intel SpeedStep submenu Mode and CPU features Select to display Displays system memory configuration detected submenu during POST ...
Page 149
... Core Multi-processing sets the state of logical processor cores in a package. [Disabled] sets only Enabled/Disable logical processor core 0 as enabled in each processor package. Intel® Virtualization Technology allows a platform to run multiple operating systems and applications in independent partitions. Enabled/Disabled Note: A change to this option requires the system to be powered off and then back on before the setting will take effect ...
Page 150
... To access this submenu, select Advanced on the menu bar, then Serial Port submenu. The Serial Port options are given in Table 57. Serial port submenu options Feature Address IRQ ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 150 Options Displays current memory bus speed. MPCBL0050 supports Info Only only 533MT/s memory speed Displays the RAS configuration information ...
Page 151
... Controller [Ports A & B) Enabled/ Enables Option ROM for fabric interface (PICMG) Gigabit Ethernet LAN Disabled Controller [Ports & F) Info Only Displays MAC addresses of all available Gigabit Ethernet LAN ports Intel NetStructure Description Description ® MPCBL0050 Single Board Computer Technical Product Specification 151 ...
Page 152
... PCI-Ex x8/PCI-Ex Choose the PCI-Ex link with between MCH and AdvancedMC ports. x4 Intel® I/O Acceleration Technology (I/OAT*) accelerates TCP/IP processing for onboard NICs, delivers data-movement efficiencies Enabled/ across the entire server platform, and minimizes system overhead. Disabled To utilize this feature OS driver must support new DMA engine embedded into the MCH ...
Page 153
... When booting next time EFI BIOS will try booting from Enabled/Disabled subsequent device on the booting list. Refer to “Progressive Boot Mechanism” on page 144 Note: Requires OS support or Intel Management Software If the OS watchdog timer is enabled, this is the system action taken if the watchdog timer expires. Power Off/Reset [Reset] - System performs a reset ...
Page 154
... Boot Options menu Feature Boot Timeout Boot Option #X Quite Boot POST Error Pause Hard Disk Order CDROM Order Network Device Order ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 154 Options None Hardware Select flow control for console redirection Software 115200 ...
Page 155
... List of available Network bootable Choose fourth network device devices List of available Network bootable Choose fifth network device devices List of available Network bootable Choose sixth network device devices Intel NetStructure Table 65. Description Table 66. Description ® MPCBL0050 Single Board Computer Technical Product Specification 155 ...
Page 156
... Discard Changes and Exit Save Changes Discard Changes Restore Defaults Save As User Default Values Load User Default Values ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 156 Table 67. Description Exit EFI BIOS Setup Utility after saving changes. The system will reboot if required ...
Page 157
... Processor 02 Failed FRB-3 Timer 8160 Processor 01 unable to apply Microcode update 8161 Processor 02 unable to apply Microcode update 8170 Processor 01 failed Self Test (BIST) 8171 Processor 02 failed Self Test (BIST) September 2007 Order Number: 318146-001 ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 157 ...
Page 158
... Mouse component encountered a controller error 9266 Local console component encountered a controller error 9268 Local console component encountered an output error ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 158 MPCBL0050—EFI BIOS Error Messages and Checkpoints Order Number: 318146-001 September 2007 ...
Page 159
... A421 PCI component encountered a SERR error A5A0 PCI Express component encountered a PERR error A5A1 PCI Express component encountered a SERR error A5A4 PCI Express IBIST error September 2007 Order Number: 318146-001 ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 159 ...
Page 160
... This code is useful for determining the point where an error occurred. Port 80h POST codes can be retrieved from IPMC with an OEM IPMI command. Refer to Table 46, “Intel OEM commands (net function 0x30h)” on page hang, Port 80h can be retrieved remotely from the chassis management module. ...
Page 161
... Booting from boot option 8 Booting from boot option 9 Booting from boot option A Booting from boot option B Booting from boot option C Booting from boot option D Booting from boot option E Booting from boot option F ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 161 ...
Page 162
... Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 162 MPCBL0050—EFI BIOS Error Messages and Checkpoints Description Permanent memory found Entered EFI driver execution phase (DXE) Started connecting drivers Waiting for user input ...
Page 163
... IPMI v2.0 based, SOL-enabled blade, thus providing a virtual remote terminal server for accessing the blade’s serial port character stream. 9.1 References • Intelligent Platform Management Interface Specification v2.0, dated June 1, 2004 • AES - Advanced Encryption Standard, fips197/fips-197.pdf 9.2 SOL Architecture The SOL implementation on the Intel NetStructure definition in Section 15 of the IPMI v2 ...
Page 164
... This architecture requires the following components to perform Serial over LAN operations: • SOL-capable firmware executing on the Intelligent Platform Management Controller (IPMC). The IPMC also provides a dedicated SMBus connection to the base interface Ethernet controller. This connectivity is not shared with IPMB-0 or any other I SMBus/IPMB connections that the IPMC may provide on the blade for hardware management ...
Page 165
... RMCP+ sessions. The SOL feature, however, is disabled by default. The IP address to be used by IPMC can be configured during initial setup of the blade in the system. September 2007 Order Number: 318146-001 Figure 37, the IPMI controller on the blade provides a ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 165 ...
Page 166
... Reference Configuration Script Intel provides an SOL reference script (reference_cfg) that sets up the various parameters required for SOL operation. The SOL configuration reference script (reference_cfg) sends a sequence of IPMI commands to configure an SBC to enable the SOL feature. This script can be executed on a payload CPU for local configuration node that has network connectivity to the target SBC ...
Page 167
... ARP configuration • User ID and password to authenticate access • Channel, user, payload, and SOL privilege levels The configuration utility is referring to the reference_cfg script described above. September 2007 Order Number: 318146-001 ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 167 ...
Page 168
... If reference_cfg cannot find the library in any of these locations, it terminates with an error message. When running the reference script on a remote node over RMCP via a shelf manager, RMCP to IPMB bridging must be enabled on the shelf manager. In the case of the Intel ® NetStructure MPCMM0001/0002 Chassis Management Module, the following ...
Page 169
... Specifies which MAC address should be used to configure the blade. MAC address is given -m in the form of ##:##:##:##:##:## -H RMCP- address or host name of the shelf manager used to bridge RMCP messages to IPMB. September 2007 Order Number: 318146-001 Table Meaning ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 70. 169 ...
Page 170
... Choose Save and Exit. Note: If the default EFI BIOS baud rate is changed to a baud rate other than 9600, then the reference_cfg script will need to be changed to match the same baud rate. ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 170 Meaning 1.3.6.6 or later MPCBL0050— ...
Page 171
... Here you are adding kernel line does not already exist. e. Type :wq! September 2007 Order Number: 318146-001 option) r lilo (see Figure console=ttyS0,9600n8 rhgb quiet to save the changes. Intel NetStructure command wq! 40). to the end of the ® MPCBL0050 Single Board Computer Technical Product Specification 171 ...
Page 172
... The sbcutils RPM is installed via the following procedure. For complete details on sbcutils installation, refer to the sbcutilities RPM install procedure on the MPCBL0050 product page at http://www.intel.com. 1. Copy the RPM to the target blade. Ensure that the RPM copied is for the particular OS installed on the target blade. ...
Page 173
... IPMC through the KCS interface. Execute this command to configure SOL on the target blade: reference_cfg -I kcs -g -i <SOL Target IP Addr> — Script executed on the Intel CMM. Communication is from CMM to target blade through IPMB. This requires the MPCMM0001 or MPCMM0002 CMM and firmware version 6.1.0.2779 or later. ...
Page 174
... Linux* computer and that computer can be located anywhere in the network. In the example described in this section, ipmitool is running on another blade in the same chassis. ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 174 -g -i <SOL Target IP Addr> ...
Page 175
... If the computer that ipmitool was just installed on has a local IPMC, the ipmitool installation can be tested by typing: correctly, the response should format similar to September 2007 Order Number: 318146-001 service network restart http://ipmitool.sourceforge.net/ ipmitool-1.8.7.tar.gz ipmitool raw 6 1 Intel NetStructure . If ipmitool is running ® MPCBL0050 Single Board Computer Technical Product Specification 175 ...
Page 176
... RMCP+ Cipher Suites Cipher Suite Priv Max 9.8.2.5 Ending an SOL Session To use the front panel serial console port on the target blade, end the SOL session. ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 176 ping soluserpassword sol activate Use ~? for help] ...
Page 177
... The SOL client utility (ipmitool) can be compiled to work with any Linux* OS. September 2007 Order Number: 318146-001 just once, this symbol does not appear on the ~ the SOL session deactivates on the SOL target blade. To make sure Intel NetStructure ® MPCBL0050 Single Board Computer Technical Product Specification 177 ...
Page 178
... Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 178 MPCBL0050—Serial Over LAN September 2007 Order Number: 318146-001 ...
Page 179
... This mode can be used for automatic (programmatic) invocations of the update utility. To update EFI BIOS automatically without human intervention or responses to prompts, execute the following command: ./flashlnx -q -b MPCBL0050_EFI_BIOS_XXXXXX.CAP”. September 2007 Order Number: 318146-001 ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 179 ...
Page 180
... Copying BIOS.bin from the SBC 1. Copy the flashlnx utility to the SBC. This SBC is the one with custom BIOS options that will be used to update other SBCs. ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 180 MPCBL0050—Firmware Update Utilities Command - This is the original FWH images before an upgrade ...
Page 181
... BIOS.cap 4. Upon completion, perform a reset to ensure that the new settings and BIOS are loaded. Caution: To ensure that the BIOS.bin file is not corrupted, Intel strongly suggests performing these steps before major deployment of any SBCs running in a live network environment. 10.2.5 ...
Page 182
... Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 182 Message Label MSG_NONE "No error" MSG_INVALID_ARG "Invalid argument count" _COUNT MSG_INVALID_ARG "Invalid argument" UMENT MSG_INVALID_SWI "Invalid switch" ...
Page 183
... MSG_ISIS_INVALID "Invalid ISIS size" _SIZE MSG_ISIS_INVALID "Invalid ISIS checksum" _CHECKSUM MSG_UNRECOGNIZE "Unrecognized sysid (0x%x)" D_SYSID MSG_DIAG_NOT_FO "DIAG header not found" UND Intel NetStructure Message Text ® MPCBL0050 Single Board Computer Technical Product Specification 183 ...
Page 184
... Software] Flash Development Toolkit V.X.XX”. This Renesas toolkit can be downloaded from: download_search_results.jsp&fp=/support/downloads/ download_results&layerId=1050 6. Create a new project workspace named “MPCBL0050BootBlock”. See ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 184 Message Label MSG_INSUFFICIENT " ...
Page 185
... Firmware Update Utilities—MPCBL0050 Figure 41. Creating a new project workspace a. Select “Generic Boot Device” at the bottom of the pull-down menu. See Figure 42. Figure 42. Selecting a boot device September 2007 Order Number: 318146-001 ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 185 ...
Page 186
... Figure 43. Selecting a COM port c. After selecting a COM port, Renesas* attempts to query the device. The following dialog is displayed. See Figure 44. Query device ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 186 MPCBL0050—Firmware Update Utilities Figure 44. Order Number: 318146-001 Figure 43 ...
Page 187
... Checksum”. Verify the checksum of the file matches the checksum of the device. 12. Exit the program. 13. Eject blade or power down (including standby power) the SBC. 14. Change the DIP switches to default position - ALL OFF September 2007 Order Number: 318146-001 45. Length : 0x00000A00 Length : 0x00000080 Intel NetStructure ® MPCBL0050 Single Board Computer Technical Product Specification 187 ...
Page 188
... Remove Existing Packages Before installing the RPM on a host system (Single Board Computer), verify that a different version of the sbcutils RPM is not currently installed. ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 188 MPCBL0050—Firmware Update Utilities 203. The rest of the steps in Section 10.6.7, “ ...
Page 189
... RMCP bridge communication. Furthermore, if the shelf manager supports filtering and privilege settings for individual IPMI commands, make sure that the IPMI September 2007 Order Number: 318146-001 ########################################### [100%] ########################################### [100%] Intel NetStructure ® MPCBL0050 Single Board Computer Technical Product Specification 189 ...
Page 190
... Online Update Open Area Online Update Write Area Online Update Close Area Online Update Register Update Online Update Capture Rollback Image ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 190 Table 74 are not filtered and are set to the indicated privilege ...
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... Not all SBCs support this feature. 10.5.2 Configuring the Intel NetStructure This section describes the procedure to configure the Intel NetStructure 0002 Chassis Management Module (CMM) to support RMCP bridging. The CMM filters individual IPMI commands for bridging based on the /etc/cmdPrivillege.ini CMM configuration file. (Note that the double “l” in the filename is spelled this way on purpose ...
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... Single Board Computer. This tool also can update FRU and SDR information on the SBC and the RTM. 10.6.1 Communication Interfaces Graphical examples of the communication interfaces used for firmware updates are provided in this section. ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 192 MPCBL0050—Firmware Update Utilities September 2007 Order Number: 318146-001 ...
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... KCS bridge - local communication from CPU to local IPMC bridged to RTM Figure 48. RMCP bridge - remote communication to shelf manager bridged to IPMC Figure 49. RMCP double bridge - remote communication to shelf manager bridged to IPMC, then bridged to the RTM September 2007 Order Number: 318146-001 ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 193 ...
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... FPGA version then the one running on the board, the new FPGA will be loaded. Due to FPGA serving major functionalities on the payload the board will be automatically rebooted in order to assure proper board operation. ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 194 MPCBL0050— ...
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... The IPMC needs to be reset for the new firmware image to be transferred to the IPMC from Staged Region (A). ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 195 ...
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... MPRTM0050_NNN.fru - RTM FRU update For example, here is the IPMC firmware update for version 1.02.00: • MPCBL0050_010200.hex Here is an example IPMC FRU update for version 1.01: • MPCBL0050_101.fru ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification 196 MPCBL0050—Firmware Update Utilities Actions ...
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... Most options are common to all utilities. These options and arguments are described in Table 76. September 2007 Order Number: 318146-001 198. ® Intel NetStructure MPCBL0050 Single Board Computer Technical Product Specification Table 76, 197 ...
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... LAN connection to a shelf manager that is configured with an RMCP bridge. • ipmb denotes IPMI over the IPMB bus. Use this interface only if the executable is being run on the shelf manager (Intel NetStructure Chassis Management Module). If omitted, kcs is assumed. User name. May characters. ...
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... SBC. The IPMC on that SBC is targeted. • The value bladeN can range from 1–14, inclusive determining which SBC to use in the chassis. • The IPMB to physical slot mapping used in the Intel NetStructure Table 79, “Mapping of physical slot to IPMB address in Intel NetStructure page 232 ...
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... RMCP bridging. Auto mode is default so by omitting the -M option, auto is assumed. When using the sbcupdate utility over RMCP bridge with Intel NetStructure MPCMM0001/0002 Chassis Management Module: • Check that the CMM firmware version is 6.1.1.x or higher. ...