AD8152-EVAL Analog Devices Inc, AD8152-EVAL Datasheet

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... Digital Video (HDTV) Data Storage Networks GENERAL DESCRIPTION AD8152 is a member of the Xstream line of products and is a breakthrough in digital switching, offering a large switch array (34 × 34) on very little power, typically 2.0 W. Additionally, it operates at data rates up to 3.2 Gbps per port, making it suitable for Sonet/SDH OC-48 with Forward Error Correction (FEC). The AD8152’ ...

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... AD8152 ELECTRICAL CHARACTERISTICS Parameter DYNAMIC PERFORMANCE Max Data Rate/Channel (NRZ) Channel Jitter RMS Channel Jitter Propagation Delay Propagation Delay Match Output Rise/Fall Time INPUT CHARACTERISTICS Input Voltage Swing Input Voltage Range Input Bias Current Input Capacitance OUTPUT CHARACTERISTICS Output Voltage Swing ...

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... Temporarily exceeding this limit may cause Model AD8152JBP AD8152-EVAL CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8152 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...

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... AD8152 VEE VEE VEE VEE VCC B VEE VEE VEE VEE VCC C VEE VEE D4 D5 O16N D O16P RESET N/C N I17P I17N VCC G I19P I19N I18N I18P H VTTI VTTI I20P I20N J I22P I22N I21N I21P K VTTI VTTI I23P I23N L I25P I25N I24N I24P ...

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... F19 RE F20 VCC G1 IN02P G2 IN02N G3 IN01N G4 IN01P G17 IN18P G18 IN18N –5– AD8152 Type Description I/O High Speed Output Complement I/O High Speed Output I/O High Speed Output Complement I/O High Speed Output I/O High Speed Output Complement Control Input Address Pin (MSB) ...

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... AD8152 Ball Mnemonic Type Description G19 IN19N I/O High Speed Input Complement G20 IN19P I/O High Speed Input H1 VTTI Power Input Termination Supply H2 VTTI Power Input Termination Supply H3 IN03P I/O High Speed Input H4 IN03N I/O High Speed Input Complement H17 IN20N ...

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... Y10 OUT25P Y11 VCC Y12 OUT28P Y13 VTTO Y14 OUT31P Y15 VTTO Y16 VCC Y17 VEE Y18 VEE Y19 VEE Y20 VEE –7– AD8152 Description Power Output Termination Supply Power Positive Supply Power Negative Supply Power Negative Supply Power Negative Supply ...

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... AD8152–Typical Performance Characteristics 23 PRBS 2 –1; Differential Output Swing = 800 mV p-p; R 80ps/DIV TPC 1. Eye Pattern 3.2 Gbps PEAK-PEAK JITTER = 35ps STD DEV = 5.1ps 20ps/DIV TPC 2. Jitter @ 3.2 Gbps 1.2ns/DIV TPC 3. Response, 3.2 Gbps, 32-Bit Pattern 1111 1111 0000 0000 1010 1010 1100 1100 (2.5 V Supply, VCC = VTTI = VTTO, Data Rate = 3.2 Gbps ...

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... TPC 11. Crosstalk, 3.2 Gbps, Attack Signal OFF (See TPC 25) 3.0 3.5 4.0 TPC 12. Crosstalk, 3.2 Gbps, Attack Signal ON (See TPC 25) –9– AD8152 –0.1 0 0.1 0.2 0.3 UNIT INTERVAL TPC 10. Bit Error Rate vs. Unit Interval PEAK-PEAK JITTER = 35ps STD DEV = 5.6ps 80ps/DIV PEAK-PEAK JITTER = 46ps STD DEV = 6 ...

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... AD8152 1.5 Gbps 40 3.2 Gbps TEMPERATURE – C TPC 13. Single Point Jitter vs. Temperature 120 100 80 60 PEAK–PEAK JITTER 40 20 STANDARD DEVIATION INPUT AMPLITUDE – mV TPC 14. Jitter vs. Single-Ended Input Amplitude 180 INPUT AMPLITUDE = 50mV p-p 160 140 120 100 @2. 0.5 0.8 1.1 1 ...

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... BIN WIDTH = 5ps 725 700 675 650 625 600 700 725 750 –11– 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 SUPPLY VOLTAGE – V TPC 21. Propagation Delay vs. Supply MEASURED IDEAL CODE OUT TPC 22. I vs. I Code OUT OUT AD8152 3.6 3.8 ...

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... GENERATOR #2 DATA OUT –6dB DATA OUT –6dB TRIGGER OUT ATTACK SIGNAL APPLIED TO IN25. IN25 BROADCAST TO ALL OUTPUTS EXCEPT OUT27. TWO SEPARATE PATTERN GENERATORS USED TO PROVIDE INPUT PATTERN TO AD8152. OUTPUTS NOT CONNECTED TO OSCILLOSCOPE ARE TERMINATED WITH EXTERNAL 50 VCC VTTI VTTO IN##P OUT##P ...

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... Write Enable. Write D5:D0 data into first rank register addressed by A6:A0. Single-Output Readback. Second rank register data for output A6:A0 appears on D5:D0. Global Update. Copy all first rank data into second rank registers. Transparent Write and Update. D5:D0 immediately control programming. Use RE as gating signal. –13– AD8152 Data Pins ...

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... AD8152 A[6:0]INPUTS D[5:0]INPUTS Symbol Parameter t Setup Time Chip Select to Write Enable CSW t Address to Write Enable ASW t Data to Write Enable DSW t Hold Time Chip Select from Write Enable CHW t Address from Write Enable AHW t Data from Write Enable DHW t Width of Write Enable Pulse ...

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... DATA DATA {ADDR 2} {ADDR 1} t CSR t t RDE AA Figure 4b. Second Rank Readback Cycle Table VIII. Second Rank Readback Cycle Conditions VCC = 3.3 V –15– INPUT {DATA 2} t CHU t WHU Min Typ Max = CHR t RHA t RDD Min Typ Max AD8152 Unit Unit ...

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... Width of Reset Pulse TW CONTROL INTERFACE The AD8152 control interface receives and stores the desired connection matrix and output levels for the 34 input and 34 output signal pairs. The interface consists of 34 rows of double-rank 6-bit latches, one for each output. The 6-bit data-word stored in these latches indicates to which (if any) of the 34 inputs the output will be connected, as well as the full-scale output current ...

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... WE UPDATE Figure 6. Programming Waveforms Input/Output Coupling The AD8152 has internal 50 W termination resistors for each single-ended input and output. This can also provide a 100 W termination for a 100 W differential transmission line. All of the input termination resistors connect to one common point called VTTI. Similarly, each of the output termination resistors connects to one common point called VTTO ...

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... AD8152 inputs and the amplitude of the input signal. The operating input range of the AD8152 extends from VCC + 0 0.8 V above VEE. The total range that will be occupied by the input signal will be its average value (as established by the voltage applied to VTTI) plus or minus one half the single-ended swing of the signal ...

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... There are several sections of the AD8152 that draw varying power depending on the supply voltages, the type of I/O coupling used, and the status of the AD8152 operation. Figure 9 shows a block diagram of these sections. These are described briefly below and then in detail later in the data sheet. Table X summarizes the power consumption of each section and is a useful guide as the following sections are reviewed ...

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... OL and the power for all 34 channels is 1. VTTO = 2.5 V, then the additional power is given ¥ [(2.5 V – (16 mA ¥ 25 W)] = 33.6 mW. Thus, the total AD8152 power dissipation for this output is 37.6 mW. If all 34 outputs are enabled with the same I dissipation is 1.28 W. Thus it can be seen that the outputs are the major contributor to the power dissipation ...

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... SMA connectors. The remain- ing four inner metal layers are for the four AD8152 supply and digital control signal routing. From top to bottom the four supply layers are VTTO, VCC, VEE, and VTTI ...

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... Wider microstrip is desirable for reducing eye height loss versus long traces; how- ever, the routing will be more difficult as the AD8152 is approached. The wide microstrip would have to be necked down in width in order to be routed into the BGA. The necking will increase trace impedance and therefore induce more signal reflection problems ...

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... Figure example of a loop-through test setup using a posi- tive supply. In this case, the test signal goes through the AD8152 twice possible to loop through multiple times if desired, but jitter will increase with number of loop-throughs. The first input from the generator and the last output to a scope must be ac-coupled ...

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... Figure 17 shows an evaluation board control panel from a PC display. A single screen allows control of all the programmable functions of the AD8152. The programming modes are listed in the Mode box. Select either I/O Programming or Current Programming by selecting the appropriate radio button. These will allow either programming the switch matrix or the output currents one at a time ...

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... REV. A Figure 18. Evaluation Board Top Side Signals –25– AD8152 ...

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... AD8152 Figure 19. Evaluation Board Bottom Side Signals, View from Top –26– REV. A ...

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... Figure 20. Evaluation Board VCC Layer, View from Top REV. A –27– AD8152 ...

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... AD8152 Figure 21. Evaluation Board VEE Layer, View from Top –28– REV. A ...

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... Figure 22. Evaluation Board VTTI Layer, View from Top REV. A –29– AD8152 ...

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... AD8152 Figure 23. Evaluation Board VTTO Layer, View from Top –30– REV. A ...

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... COPLANARITY REV. A OUTLINE DIMENSIONS 256-Ball Grid Array [SBGA] (BP-256) Dimensions shown in millimeters 1.27 24.13 REF 27.00 BSC 24.13 REF BOTTOM 0.90 0.75 SEATING 0.60 PLANE 0.25 MIN BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO-192-BAL-2 –31– AD8152 A1 CORNER ...

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... AD8152 Revision History Location 1/03—Data Sheet changed from REV REV. A. Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 –32– Page REV. A ...