CY7C04312BV-133BGC Cypress Semiconductor Corp, CY7C04312BV-133BGC Datasheet - Page 23

• Manufacturer Part Number: CY7C04312BV-133BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C04312BV-133BGC

• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-06027 Rev. *A
Master Reset
The QuadPort DSE device undergoes a complete reset by
taking its Master Reset (MRST) input LOW. The Master Reset
input can switch asynchronously to the clocks. A Master Reset
initializes the internal burst counters to zero, and the counter
mask registers to all ones (completely unmasked). A Master
Reset also forces the Mailbox Interrupt (INT) flags and the
Counter Interrupt (CNTINT) flags HIGH, resets the BIST
controller, and takes all registered control signals to a
deselected read state.
on the QuadPort DSE device after power-up.
Interrupts
The upper four memory locations may be used for message
passing and permit communications between ports. Table 3
shows the interrupt operation for all ports. For the 1-Mb
QuadPort DSE device, the highest memory location FFFF is
Table 3. Interrupt Operation Example
Note:
Address Counter Control Operations
Counter enable inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for the fast interleaved memory applications.
A port’s burst counter is loaded with the port’s Counter Load
pin (CNTLD). When the port’s Counter Increment (CNTINC) is
asserted, the address counter will increment on each LOW to
HIGH transition of that port’s clock signal. This will read/write
one word from/into each successive address location until
CNTINC is deasserted. Depending on the mask register state,
the counter can address the entire memory array and will loop
back to start. Counter Reset (CNTRST) is used to reset the
Burst Counter (the Mask Register value is unaffected). When
using the counter in readback mode, the internal address
value of the counter will be read back on the address lines
when Counter Readback Signal (CNTRD) is asserted.
56. During Master Reset the control signals will be set to a deselected read state: CE
Set Port 1 INT
Reset Port 1 INT
Set Port 2 INT
Reset Port 2 INT
Set Port 3 INT
Reset Port 3 INT
Set Port 4 INT
Reset Port 4 INT
CNTINCI = V
Function
IH
P1
P2
P3
P4
; CE
Flag
P1
P2
Flag
P3
P4
Flag
Flag
1I
Flag
Flag
Flag
Flag
= V
[56]
IL.
The “I” suffix on all these signals denotes that these are the internal registered equivalent of the associated pin signals.
A Master Reset must be performed
A
0P1–15P1
FFFD
FFFC
FFFF
FFFE
X
X
X
X
Port 1
INT
H
X
X
X
X
X
X
L
P1
[31]
A
0P2–15P2
FFFE
FFFD
FFFC
FFFF
X
X
X
X
Port 2
the mailbox for Port 1, FFFE is the mailbox for Port 2, FFFD is
the mailbox for Port 3, and FFFC is the mailbox for Port 4.
Table 3 shows that in order to set Port 1 INT
any other port to address FFFF will assert INT
of FFFF location by Port 1 will reset INT
port writes to the other port’s mailbox, the Interrupt flag (INT)
of the port that the mailbox belongs to is asserted LOW. The
Interrupt is reset when the owner (port) of the mailbox reads
the contents of the mailbox. The interrupt flag is set in a
flow-through mode (i.e., it follows the clock edge of the writing
port). Also, the flag is reset in a flow-through mode (i.e., it
follows the clock edge of the reading port).
Each port can read the other port’s mailbox without resetting
the interrupt. If an application does not require message
passing, INT pins should be treated as no-connect and should
be left floating. When two ports or more write to the same
mailbox at the same time INT will be asserted but the contents
of the mailbox are not guaranteed to be valid.
Figure 1 provides a block diagram of the readback operation.
Table 2 lists control signals required for counter operations.
The signals are listed based on their priority. For example,
Master Reset takes precedence over Counter Reset, and
Counter Load has lower priority than Mask Register Load
(described below). All counter operations are independent of
Chip Enables (CE
operation is performed the data I/Os are three-stated (if CEs
are active) and one-clock cycle (no-operation cycle) latency is
experienced. The address will be read at time t
rising edge of the clock following the no-operation cycle. The
read back address can be either of the burst counter or the
mask register based on the levels of Counter Read signal
(CNTRD) and Mask Register Read signal (MKRD). Both
signals are synchronized to the port's clock as shown in
Table 2. Counter read has a higher priority than mask read.
0I
= LBI = UBI = R/WI = MKLDI = MKRDI = CNTRDI = CNTRSTI = CNTLDI =
INT
X
X
H
X
X
X
X
L
P2
A
0P3–15P3
FFFD
FFFC
FFFF
FFFE
0
X
X
X
X
and CE
Port 3
1
). When the address readback
INT
H
X
X
X
X
L
X
X
P3
CY7C04312BV
CY7C04314BV
CY7C0430BV
A
P1
0P4–15P4
FFFF
FFFE
FFFD
FFFC
HIGH. When one
P1
X
X
X
X
P1
Port 4
Page 23 of 37
flag, a write by
LOW. A read
CA2
from the
INT
H
X
X
X
X
X
X
4
L
P