AD8315ARM-REEL Analog Devices Inc, AD8315ARM-REEL Datasheet - Page 14

• Manufacturer Part Number: AD8315ARM-REEL
• Manufacturer: Analog Devices Inc

Specifications of AD8315ARM-REEL

• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -30C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Not Compliant

AD8315
First, the summed detector currents are written as a function of
the input
where:
I
exact average value is extracted through the subsequent
integration step.
I
decade (that is, 5.75 μA/dB).
V
V
is dependent on waveform but is 316 μV rms (−70 dBV) for a
sine wave input.
Now the current generated by the setpoint interface is simply
The difference between this current and I
loop filter capacitor C
on this capacitor, V
current:
The control output V
gain of the output buffer is ×1.35. In addition, an offset voltage
is deliberately introduced in this stage; this is inconsequential
because the integration function implicitly allows for an
arbitrary constant to be added to the form of Equation 6. The
polarity is such that V
value of V
practice, the V
condition unless the control loop through the power amplifier
is present. In other words, the AD8315 seeks to drive the RF
power to its maximum value whenever it falls below the
setpoint. The use of exact integration results in a final error that
is theoretically 0, and the logarithmic detection law would
ideally result in a constant response time following a step
change of either the setpoint or the power level, if the power-
amplifier control function were likewise linear in dB. However,
this latter condition is rarely true, and it follows that in practice,
the loop response time depends on the power level, and this
effect can strongly influence the design of the control loop.
DET
SLP
IN
Z
is the effective intercept voltage, which, as previously noted,
is the current-mode slope and has a value of 115 μA per
is the input in V rms.
is the partially filtered demodulated signal, whose
I
I
V
=
DET
SET(4)
FLT
V
= I
(s) = ( I
SET
= V
SET
SLP
4.15
greater than the equivalent value of V
SET
log
APC
SET
/415 kΩ
10
kΩ
output rails to the positive supply under this
− I
FLT
( V
APC
−
DET
, is the time integral of the difference
FLT
sC
APC
IN
I
/ V
. It follows that the voltage appearing
)/ sC
SLP
FLT
is slightly greater than this, because the
rises to its maximum value for any
Z
)
log
FLT
10
(
V
IN
V
Z
DET
)
is applied to the
IN
. In
Rev. C | Page 14 of 24
(3)
(4)
(5)
(6)
Equation 6 can be restated as
where V
having a value of 480 mV/decade, and T is an effective time
constant for the integration, being equal to 4.15 kΩ × C
the resistor value comes from the setpoint interface scaling
Equation 4 and the factor 1.35 arises because of the voltage gain
of the buffer. Therefore, the integration time constant can be
written as
To simplify our understanding of the control loop dynamics,
begin by assuming that the power amplifier gain function is
actually linear in dB, and for the moment, use voltages to
express the signals at the power amplifier input and output.
Let the RF output voltage be V
Furthermore, to characterize the gain control function, this
form is used
where:
G
V
While few amplifiers conform so conveniently to this law, it
provides a clearer starting point for understanding the more
complex situation that arises when the gain control law is less ideal.
This idealized control loop is shown in Figure 34. With some
manipulation, it is found that the characteristic equation of this
system is
where:
k is the coupling factor from the output of the power amplifier
to the input of the AD8315 (for example, ×0.1 for a 20 dB coupler).
T
This is quite easy to interpret. First, it shows that a system of
this sort exhibits a simple single-pole response, for any power
level, with the customary exponential time domain form for
either increasing or decreasing step polarities in the demand
level V
final value of the control voltage V
fixed factors:
O
O
GBC
is a modified time constant (V
is the gain of the power amplifier when V
T = 3.07 C
V
V
is the gain scaling.
V
V
APC
PA
APC
APC
SET
SLP
=
or the carrier input V
( )
( )
(
s
s
is the volts-per-decade slope from Equation 1,
G
τ
O
=
=
=
V
∞
V
FLT
(
CW
V
) (
SET
SET
=
in μs, when C is expressed in nF
10
V
−
V
(
V
SET
V
APC
GBC
SLP
V
V
)
GBC
GBC
log
sT
V
SLP
)
)
10
PA
CW
V
−
(
and let its input be V
V
GBC
SLP
1
. Second, it reveals that the
V
APC
IN
+
GBC
/V
−
sT
V
is determined by several
log
SLP
O
Z
log
)
)T.
10
10
(
APC
(
kG
kG
O
= 0.
O
V
V
CW
CW
CW
V
FLT
V
.
Z
Z
/1.35;
)
)
(11)
(10)
(7)
(8)
(9)