XC5VSX50T-1FF665C Xilinx Inc, XC5VSX50T-1FF665C Datasheet - Page 203

• Manufacturer Part Number: XC5VSX50T-1FF665C
• Description: FPGA Virtex®-5 Family 52224 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-1FF665C

• Package: 665FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 52224
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 360
• Ram Bits: 4866048
• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Total Ram Bits: 4866048
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Timing Characteristics
Figure 5-26
X-Ref Target - Figure 5-26
•
•
•
At time T
CE input of the slice register.
At time T
become valid-High at the D input of the slice register and is reflected on either the
AQ, BQ, CQ, or DQ pin at time T
At time T
becomes valid-High, resetting the slice register. This is reflected on the AQ, BQ, CQ,
or DQ pin at time T
illustrates the general timing characteristics of a Virtex-5 FPGA slice.
CEO
DICK
SRCK
AQ/BQ/CQ/DQ
AX/BX/CX/DX
before clock event (1), the clock-enable signal becomes valid-High at the
SR (RESET)
Figure 5-26: General Slice Timing Characteristics
before clock event (1), data from either AX, BX, CX, or DX inputs
before clock event (3), the SR signal (configured as synchronous reset)
(DATA)
(OUT)
CKO
CLK
CE
www.xilinx.com
after clock event (3).
1
CKO
T
T
CEO
DICK
after clock event (1).
T
CKO
2
3
CLB / Slice Timing Models
T
ug190_5_26_050506
SRCK
T
CKO
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