4302-00 Peregrine Semiconductor, 4302-00 Datasheet - Page 7

• Manufacturer Part Number: 4302-00
• Description: KIT EVAL FOR 4302 RF DSA
• Manufacturer: Peregrine Semiconductor
• Series: UltraCMOS™r
• Type: Attenuatorr

Specifications of 4302-00

• Frequency: 0Hz ~ 4GHz
• For Use With/related Products: PE4302
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 1046-1001; 4302-0

PE4302
Product Specification
Evaluation Kit
The Digital Attenuator Evaluation Kit board was
designed to ease customer evaluation of the
PE4302 Digital Step Attenuator.
J9 is used in conjunction with the supplied DC
cable to supply VDD, GND, and –VDD. If use of
the internal negative voltage generator is desired,
then connect –VDD (Black banana plug) to
ground. If an external –VDD is desired, then apply
-3V.
J1 should be connected to the parallel port of a
PC with the supplied ribbon cable. The evaluation
software is written to operate the DSA in serial
mode, so Switch 7 (P/S) on the DIP switch SW1
should be ON with all other switches off. Using the
software, enable or disable each attenuation
setting to the desired combined attenuation. The
software automatically programs the DSA each
time an attenuation state is enabled or disabled.
To evaluate the Power Up options, first disconnect
the parallel ribbon cable from the evaluation
board. The parallel cable must be removed to
prevent the PC parallel port from biasing the
control pins.
During power up with P/S=1 high and LE=0 or P/
S=0 low and LE=1, the default power-up signal
attenuation is set to the value present on the six
control bits on the six parallel data inputs (C0.5 to
C16). This allows any one of the 64 attenuation
settings to be specified as the power-up state.
During power up with P/S=0 high and LE=0, the
control bits are automatically set to one of four
possible values presented through the PUP
interface. These four values are selected by the
two power-up control bits, PUP1 and PUP2, as
shown in the Table 6.
Resistor on Pin 1 & 3
A 10 kΩ resistor on the inputs to Pin 1 & 3 (Figure
16) will eliminate package resonance between the
RF input pin and the two digital inputs. Specified
attenuation error versus frequency performance is
dependent upon this condition.
Document No. 70-0056-04 │ www.psemi.com
SMA
J4
Figure 15. Evaluation Board Layout
Peregrine Specification 101/0112
Figure 16. Evaluation Board Schematic
Peregrine Specification 102/0144
Note: Resistors on pins 1 and 3 are required to avoid package
1
DATA
©2003-2008 Peregrine Semiconductor Corp. All rights reserved.
resonance and meet error specifications over frequency.
C16
Z=50 Ohm
10k
10k
CLK
LE
VDD
1
2
3
4
5
C16
RFin
DATA
CLK
LE
C0.5
PUP1
C1
100 pF
MLPQ4X4
PUP2
U1
C2
Vss/GND
RFout
C4
GND
C8
PS
15
14
13
12
11
C8
PS
Z=50 Ohm
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