PIC24FV32KA304-I/PT Microchip Technology, PIC24FV32KA304-I/PT Datasheet - Page 214

• Manufacturer Part Number: PIC24FV32KA304-I/PT
• Description: MCU 32KB FLASH 2KB RAM 44-TQFP
• Manufacturer: Microchip Technology

Specifications of PIC24FV32KA304-I/PT

• Processor Series: PIC24FV
• Core: PIC
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-44
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FV32KA304 FAMILY
22.1
The 12-bit A/D Converter module uses up to
43 registers for its operation. All registers are mapped
in the data memory space.
22.1.1
Depending on the specific device, the module has up to
eleven control and status registers:
• AD1CON1: A/D Control Register 1
• AD1CON2: A/D Control Register 2
• AD1CON3: A/D Control Register 3
• AD1CON5: A/D Control Register 5
• AD1CHS: A/D Sample Select Register
• AD1CHITH and AD1CHITL: A/D Scan Compare
• AD1CSSL and AD1CSSH: A/D Input Scan Select
• AD1CTMENH and AD1CTMENL: CTMU Enable
The AD1CON1, AD1CON2 and AD1CON3 registers
(Register
control the overall operation of the A/D module. This
includes
conversion clock and voltage reference sources,
selecting the sampling and conversion triggers, and
manually controlling the sample/convert sequences.
The AD1CON5 register
controls features of the Threshold Detect operation,
including its function in power-saving modes.
The AD1CHS register
channels to be connected to the S/H amplifier. It also
allows the choice of input multiplexers and the
selection of a reference source for differential
sampling.
The
(Register 22-6
registers used with Threshold Detect operations. The
status of individual bits, or bit pairs in some cases,
DS39995B-page 214
Hit Registers
Registers
Registers
AD1CHITH
A/D Control Registers
22-1,
enabling
CONTROL REGISTERS
and
Register 22-2
the
Register
(Register
and
(Register
module,
AD1CHITL
22-7) are semaphore
22-5) selects the input
and
22-4) specifically
configuring
Register
registers
22-3)
the
indicate if a match condition has occurred. AD1CHITL
is always implemented, whereas AD1CHITH may not
be implemented in devices with 16 or fewer channels.
The
Register
sequential scanning.
The AD1CTMENH/L registers
Register
CTMU during conversions. Selecting a particular
channel allows the A/D Converter to control the CTMU
(particularly, its current source) and read its data
through
implemented, whereas AD1CTMENH may not be
implemented in devices with 16 or fewer channels.
22.1.2
The module incorporates a multi-word, dual port RAM,
called ADC1BUF. The buffer is composed of at least
the same number of word locations as there are
external analog channels for a particular device, with a
maximum number of 32. The number of buffer
addresses is always even. Each of the locations is
mapped into the data memory space and is separately
addressable. The buffer locations are referred to as
ADC1BUF0 through ADC1BUFn (up to 31).
The A/D result buffers are both readable and writable.
When the module is active (AD1CON<15> = 1), the
buffers are read-only, and store the results of A/D
conversions.
(AD1CON<15> = 0), the buffers are both readable and
writable. In this state, writing to a buffer location
programs a conversion threshold for Threshold Detect
operations.
Buffer contents are not cleared when the module is
deactivated with the ADON bit (AD1CON1<15>).
Conversion results and any programmed threshold
values are maintained when ADON is set or cleared.
AD1CSSH/L
22-9) select the channels to be included for
22-11) select the channel(s) to be used by the
that
A/D RESULT BUFFERS
When
channel.
registers
 2011 Microchip Technology Inc.
the
AD1CTMENL
module
(Register 22-8
(Register 22-10
is
is
inactive
always
and
and