STM32L152CBT6 STMicroelectronics, STM32L152CBT6 Datasheet - Page 78

• Manufacturer Part Number: STM32L152CBT6
• Description: MCU ARM 128KB FLASH LCD 48LQFP
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32L152CBT6

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LFQFP
• Core: ARM Cortex M3
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-11197

Electrical characteristics
6.3.14
78/107
Communications interfaces
I
Unless otherwise specified, the parameters given in
performed under ambient temperature, f
summarized in
The line I
with the following restrictions: SDA and SCL are not “true” open-drain I/O pins. When
configured as open-drain, the PMOS connected between the I/O pin and V
but is still present.
The I
characteristics
and SCL) .
Table 42.
1. Guaranteed by design, not tested in production.
2. f
3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
2
t
C interface characteristics
w(STO:STA)
Symbol
t
t
t
t
t
w(SCLH)
w(SCLL)
t
su(SDA)
t
t
su(STO)
to achieve fast mode I²C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I²C
fast mode clock.
period of SCL signal.
undefined region of the falling edge of SCL.
t
t
t
su(STA)
h(SDA)
PCLK1
r(SDA)
h(STA)
r(SCL)
f(SDA)
f(SCL)
C
2
C characteristics are described in
b
must be higher than 2 MHz to achieve standard mode I
2
C interface meets the requirements of the standard I
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
Start condition hold time
Repeated Start condition
setup time
Stop condition setup time
Stop to Start condition time
(bus free)
Capacitive load for each bus
line
I
2
C characteristics
for more details on the input/output alternate function characteristics (SDA
Table
Parameter
9.
Doc ID 17659 Rev 4
Standard mode I
PCLK1
Table
Min
250
0
4.7
4.0
4.0
4.7
4.0
4.7
(3)
frequency and V
42. Refer also to
²
Table 42
C frequencies. It must be higher than 4 MHz
1000
Max
300
400
2
C
(1)
STM32L151xx, STM32L152xx
are derived from tests
20 + 0.1C
DD
2
Fast mode I
Section 6.3.11: I/O port
C communication protocol
Min
100
0
1.3
0.6
0.6
0.6
0.6
1.3
supply voltage conditions
(4)
b
DD
2
C
900
Max
300
300
400
(1)(2)
is disabled,
(3)
Unit
s
s
pF
µs
ns
µs