DS26503L+ Maxim Integrated Products, DS26503L+ Datasheet - Page 52

• Manufacturer Part Number: DS26503L+
• Description: IC T1/E1/J1 BITS ELEMENT 64-LQFP
• Manufacturer: Maxim Integrated Products
• Type: BITS Elementr

Specifications of DS26503L+

• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency-max: -
• Output: -
• Input: -

10. I/O PIN CONFIGURATION OPTIONS
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
HW
Mode
Bit 0: Output Data Format (ODF)
Bit 1: TS I/O Select (TSIO). This bit determines whether the TS pin is an input or and output. See
Bit 2: TS Mode Select (TSM). In T1 or E1 operation, selects frame or multiframe mode for the TS pin. In 6312kHz mode,
this bit should be set = 0. See
Bit 3: Transmit Signaling Double-Wide Sync (TSDW). In T1 mode, setting this bit = 1 and setting TSIO = 1 will cause the
sync-pulse output on TS to be two clocks wide during signaling frames. In E1 or 6312kHz mode, this bit should be set = 0. See
Table
Bit 4: RLOF Output Function (RLOFF). In T1 or E1 receive mode this bit determines the function of the RLOF pin. In
6312kHz receive mode, this bit should be set = 0.
Bit 5: RS Mode Select 1(RSMS1). In T1 or E1 receive mode, this bit selects a frame or multiframe output pulse at RS pin.
IOCR.6 may be used to select other function for the RS pin.
Bit 6: RS Mode Select 2 (RSMS2). In T1 and E1 receive mode, this bit along with IOCR.5 selects the function of the RS pin.
Bit 7: Unused, must be set = 0 for proper operation
10-1.
0 = bipolar data at TPOS and TNEG
1 = NRZ data at TPOS; TNEG = 0
0 = TS is an input
1 = TS is an output
0 = frame mode
1 = multiframe mode
0 = (T1) normal sync pulses
1 = (T1) double-wide sync pulses during signaling frames
0 = receive loss of frame (RLOF)
1 = loss-of-transmit clock (LOTC)
0 = frame mode
1 = multiframe mode
T1 Mode: (when IOCR.5 set = 0)
E1 Mode: (when IOCR.5 set = 1)
0 = do not pulse double-wide in signaling frames
1 = do pulse double-wide in signaling frames
0 = RS outputs CAS multiframe boundaries
1 = RS outputs CRC4 multiframe boundaries
—
7
0
0
RSMS2
IOCR1
I/O Configuration Register 1
01h
Table
6
0
0
10-1.
RSMS1
PIN 1
RSM
5
0
RLOFF
.
4
0
0
52 of 122
TSDW
3
0
0
PIN 2
TSM
TSM
2
0
TSIO
1
0
0
Table
10-1.
ODF
0
0
0