ADN2819ACP-CML Analog Devices Inc, ADN2819ACP-CML Datasheet - Page 16

• Manufacturer Part Number: ADN2819ACP-CML
• Description: IC RECOVER CLOCK/DATA 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Clock and Data Recovery (CDR)r

Specifications of ADN2819ACP-CML

• Rohs Status: RoHS non-compliant
• Output: CML
• Frequency - Max: 2.7GHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 2.7GHz
• Input: -

ADN2819
SQUELCH MODE
When the squelch input is driven to a TTL high state, the clock
and data outputs are set to the zero state to suppress down-
stream processing. If desired, this pin can be directly driven by
the LOS (loss of signal) detector output (SDOUT). If the
squelch function is not required, the pin should be tied to VEE.
TEST MODES: BYPASS AND LOOPBACK
When the bypass input is driven to a TTL high state, the
quantizer output is connected directly to the buffers driving the
data out pins, thus bypassing the clock recovery circuit (see
Figure 21). This feature can help the system deal with
nonstandard bit rates.
NIN
PIN
VREF
50Ω
ADN2819
50Ω
+
QUANTIZER
TDINP/N
50Ω
VCC
50Ω
Figure 21. Test Modes
Rev. B | Page 16 of 24
LOOPEN BYPASS
0
1
FROM
QUANTIZER
OUTPUT
The loopback mode can be invoked by driving the LOOPEN
pin to a TTL high state, which facilitates system diagnostic
testing. This connects the test inputs (TDINP/N) to the clock
and data recovery circuit (per Figure 21). The test inputs have
internal 50 Ω terminations, and can be left floating when not in
use. TDINP/N are CML inputs and can only be dc-coupled
when being driven by CML outputs. The TDINP/N inputs must
be ac-coupled if driven by anything other than CML outputs.
Bypass and loopback modes are mutually exclusive: only one of
these modes can be used at any given time. The ADN2819 is put
into an indeterminate state if both the BYPASS and LOOPEN
pins are set to Logic 1 at the same time.
1
DATAOUTP/N
RETIMED
DATA
0
CDR
CLKOUTP/N SQUELCH
CLK