SI5315B-C-GMR Silicon Laboratories Inc, SI5315B-C-GMR Datasheet
SI5315B-C-GMR
Specifications of SI5315B-C-GMR
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SI5315B-C-GMR Summary of contents
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ERN Features Provides jitter attenuation and frequency translation between SONET/PDH ...
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Si5315 2 Rev. 0.26 ...
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T C ABLE O F ONTENTS Section 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... CKN Single-ended Input Voltage Swing Differential Input Voltage Swing Notes: 1. Refers to Si5315A speed grade. 2. Refers to Si5315B speed grade. 3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 12 – ºC) A Test Condition 3.3 V nominal 2.5 V nominal 1.8 V nominal = – ...
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... Output Voltage Low CKO Output Voltage High CKO Notes: 1. Refers to Si5315A speed grade. 2. Refers to Si5315B speed grade. 3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 12. = – ºC) A Test Condition LVPECL 100 load ...
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... Input Resistance XA Input Voltage Level Limits XA Input Voltage Swing XA Notes: 1. Refers to Si5315A speed grade. 2. Refers to Si5315B speed grade. 3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 12 – ºC) A Test Condition CMOS IO Driving into CKO ...
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... Differential Input Voltage XA/XB Level Limits Input Voltage Swing XA VPP Notes: 1. Refers to Si5315A speed grade. 2. Refers to Si5315B speed grade. 3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 12. = – ºC) A Test Condition XTAL/CLOCK = M RIN VIN ...
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... LOSn Trigger Window LOSX Trigger Window Time to Clear LOS Alarm Time to Declare LOL after LOS Time to Clear LOL after LOS Cleared t Notes: 1. Assumes N3 does not equal CKN 2. Refers to Si5315A speed grade. 3. Refers to Si5315B speed grade – ºC) A Symbol Test Condition CKN F ...
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... Holdover Initial Frequency Error Holdover Frequency Stability vs. Power Supply Holdover Frequency Deviation vs. Temperature Spurious Noise Notes: 1. Assumes N3 does not equal CKN 2. Refers to Si5315A speed grade. 3. Refers to Si5315B speed grade. = – ºC) A Symbol Test Condition RST with valid CKIN to t LOCKHW LOL 100 Hz ...
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... BWSEL [1:0] loop bandwidth settings provided in Table 7 on page 20 MHz fundamental mode crystal used as XA/XB input 2 ° Si5315A test condition 19.44 MHz (20–80%), LVPECL clock output. 6. Si5315B test condition: f =19.44 MHz 80%), LVPECL clock output. Table 5. Thermal Characteristics (V = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol Thermal Resistance ...
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V SIGNAL + Differential I/ ICM OCM SIGNAL – (SIGNAL +) – (SIGNAL – ICM OCM SIGNAL + SIGNAL – Figure 1. CKIN Voltage Characteristics DOUT, CLOUT Figure 2. Rise/Fall Time Characteristics Single-Ended V ...
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Si5315 1.1. Three-Level (3L) Input Pins (No External Resistors) External Driver Parameter Input Voltage Low Input Voltage Mid Input Voltage High Input Low Current Input Mid Current Input High Current Note: The above currents are the amount of leakage that ...
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Three-Level (3L) Input Pins (With External Resistors) External Driver One of eight resistors from a Panasonic EXB-D10C183J (or similar) resistor pack Parameter Input Low Current Input Mid Current Input High Current Note: The above currents are the amount of ...
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Si5315 Table 6. Absolute Maximum Ratings Parameter DC Supply Voltage LVCMOS Input Voltage Operating Junction Temperature Storage Temperature Range ESD HBM Tolerance (100 pF, 1.5 k); All pins except CKIN+/CKIN– ESD MM Tolerance; All pins except CKIN+/CKIN– ESD HBM Tolerance ...
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System Level Overview The Si5315 provides clock translation, jitter attenuation, and clock distribution for high-performance Synchronous Ethernet line card timing applications. The device accepts two clock inputs ranging from 8 kHz to 644.53 MHz and generates two equal frequency, ...
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Si5315 3. Functional Description 2 CKIN1+ CKIN1– CKIN2+ 2 CKIN2– LOS1 LOS2 Signal Detect LOL AUTOSEL Control CS/CA RST Bandwidth BWSEL[1:0] Control FRQSEL[3:0] Frequency Control FRQTBL 3.1. Overview The Si5315 is a jitter-attenuating precision clock multiplier for Synchronous Ethernet, SONET/SDH, ...
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PLL Performance The Si5315 provides extremely low jitter generation, a well-controlled jitter transfer function, and high jitter tolerance due to the high level of integration. 3.2.1. Jitter Generation Jitter generation is defined as the amount of jitter produced at ...
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Si5315 3.2.3. Jitter Tolerance Jitter tolerance is defined as the maximum peak-to-peak sinusoidal jitter that can be present on the incoming clock before the DSPLL loses lock. The tolerance is a function of the jitter frequency, because tolerance improves for ...
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Frequency Plan Tables For ease of use, the Si5315 is pin controlled to enable simple device configuration of the frequency plan and PLL loop bandwidth via a predefined look up table. The DSPLL has been optimized for each frequency ...
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Si5315 20 Rev. 0.26 ...
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Rev. 0.26 Si5315 21 ...
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Si5315 22 Rev. 0.26 ...
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Rev. 0.26 Si5315 23 ...
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Si5315 24 Rev. 0.26 ...
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Rev. 0.26 Si5315 25 ...
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Si5315 26 Rev. 0.26 ...
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Rev. 0.26 Si5315 27 ...
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Si5315 28 Rev. 0.26 ...
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Rev. 0.26 Si5315 29 ...
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Si5315 4.2. PLL Self-Calibration An internal self-calibration (ICAL) is performed before operation to optimize loop parameters and jitter performance. While the self-calibration is being performed, the DSPLL is being internally controlled by the self- calibration state machine. The LOL alarm ...
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Recommended Reset Guidelines Follow the recommended RESET guidelines in Table 8 when reset should be applied to a device. Pin # Si5315 Pin Name 2 FRQTBL 11 XTAL/CLOCK 22 BWSEL0 23 BWSEL1 24 FRQSEL0 25 FRQSEL1 26 FRQSEL2 27 ...
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Si5315 4.3. Input Clock Control This section describes the clock selection capabilities (manual input selection, automatic input selection, hitless switching, and revertive switching). When switching between two clocks, LOL may temporarily go high if the two clocks differ in frequency ...
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Automatic Clock Selection The AUTOSEL input pin sets the input clock selection mode as shown in Table 9. Automatic switching is either revertive or non-revertive. Setting AUTOSEL changes the CS_CA pin to an output pin ...
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Si5315 4.4. Alarms Summary alarms are available to indicate the overall status of the input signals. Alarm outputs stay high until all the alarm conditions for that alarm output are cleared. 4.4.1. Loss-of-Signal The device has loss-of-signal circuitry that continuously ...
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Holdover Mode If an LOS condition exists on the selected input clock, the device enters holdover. In this mode, the device provides a stable output frequency until the input clock returns and is validated. When the device enters holdover, ...
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Si5315 4.6. PLL Bypass Mode The Si5315 supports a PLL bypass mode in which the selected input clock is fed directly to both enabled output buffers, bypassing the DSPLL. Internally, the bypass path is implemented with high-speed differential signaling; however, ...
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High-Speed I/O 5.1. Input Clock Buffers The Si5315 provides differential inputs for the CKINn clock inputs. These inputs are internally biased to a common mode voltage [see Table 2, “DC Characteristics”] and can be driven by either a single-ended ...
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Si5315 CML/ LVDS Driver Figure 12. CML/LVDS Termination (1.8, 2.5, 3 CMOS Driver Figure 13. CMOS Termination (1.8, 2.5, 3 Si5315 C 100 40 k Si5315 ...
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Output Clock Drivers The Si5315 has a flexible output driver structure that can drive a variety of loads, including LVPECL, LVDS, CML, and CMOS formats. The signal format is selected for both CKOUT1 and CKOUT2 outputs using the SFOUT ...
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Si5315 SFOUT[1: (Output disable) Output from DSPLL Figure 16. Disable CKOUTn Structure The SFOUT [1:0] pins can also be used to disable both outputs. Disabling the output puts the CKOUTn+ and CKOUTn– pins in a high-impedance state relative ...
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Crystal/Reference Clock Input The device can use an external crystal or external clock as a reference external clock is used, it must be ac coupled. With appropriate buffers, the same external reference clock can be applied to ...
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Si5315 6.1. Crystal/Reference Clock Selection An external, low jitter 40 MHz clock or a low-cost 40 MHz fundamental mode crystal is used as part of a fixed- frequency oscillator within the DSPLL. This external X-reference on XA/XB is required for ...
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Reference Jitter Jitter on the reference input has a roughly one-to-one transfer function to the output jitter over the bandwidth ranging from 100 kHz crystal is used on the XA/XB pins, the reference ...
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Si5315 7. Power Supply Filtering This device incorporates an on-chip voltage regulator with excellent PSRR to power the device from a supply voltage of 1.8, 2.5, or 3.3 V. The device requires minimal supply decoupling and no stringent layout or ...
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Typical Phase Noise Plots The following is a typical phase noise plot. The clock input source was a Rohde and Schwarz model SML03 RF Generator. The spectrum analyzer was either an Agilent model E5052B, model E4400A or model JS-500. ...
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Si5315 9. Typical Application Circuit System Power Supply 130 130 82 82 Input Clock Sources from Telecom Backplane 130 130 82 82 ...
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Pin Descriptions: Si5315 FRQTBL AUTOSEL Pin assignments are preliminary and subject to change. Pin # Pin Name I RST 2 FRQTBL I 3 LOS1 O 4 LOS2 ...
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Si5315 Table 18. Si5315 Pin Descriptions (Continued) Pin # Pin Name I GND GND 15,19, 20,31 9 AUTOSEL I 11 XTAL/CLOCK I 12 CKIN2 CKIN2– ...
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Table 18. Si5315 Pin Descriptions (Continued) Pin # Pin Name I/O 14 DBL2_BY I 16 CKIN1 CKIN1– 18 LOL O 21 CS_CA I/O 23 BWSEL1 I 22 BWSEL0 Signal Level 3-Level Output 2 Disable/Bypass Mode Control. Controls enable ...
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Si5315 Table 18. Si5315 Pin Descriptions (Continued) Pin # Pin Name I/O 27 FRQSEL3 I 26 FRQSEL2 25 FRQSEL1 24 FRQSEL0 29 CKOUT1– CKOUT1+ 33 SFOUT0 I 30 SFOUT1 34 CKOUT2– CKOUT2 — GND ...
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Table 19. Si5315 Pull-up/Pull-down Pin # Si5315 Pull? 1 RST U 2 FRQTBL AUTOSEL XTAL CLOCK 14 DBL2_BY CS_CA BWSEL0 BWSEL1 U, D ...
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... Si5315 11. Ordering Guide Ordering Part Number Output Clock Freq Range Si5315A-C-GM 8 kHz–644.53 MHz Si5315B-C-GM 8 kHz–125 MHz Si5315-EVB 8 kHz–644.53 MHz Add the end of the device to denote tape and reel options (i.e., Si5315A-C-GMR). Note: Table 20. Any-rate Precision Clock Product Selection Guide ...
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Package Outline: 36-Pin QFN Figure 24 illustrates the package details for the Si5315. Table 21 lists the values for the dimensions shown in the illustration. Figure 24. 36-Pin Quad Flat No-Lead (QFN) Symbol Millimeters Min Nom A 0.80 0.85 ...
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Si5315 13. Recommended PCB Layout Figure 26. Ground Pad Recommended Layout 54 Figure 25. PCB Land Pattern Diagram Rev. 0.26 ...
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Table 22. PCB Land Pattern Dimensions Dimension Notes (General): 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 ...
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Si5315 14. Si5315 Device Top Mark Speed Code Product Revision G: Temperature Range ...
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... Supply Filtering” Updated Typical phase noise plot and RMS jitter table in Section 8. "Typical Phase Noise Plots” Revision 0.25 to Revision 0.26 Corrected Section 11. "Ordering Guide” Output Clock Frequency Range for Si5315B-C- kHz–125 Mhz. : Rev. 0.26 Si5315 57 ...
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