SI5324D-C-GM Silicon Laboratories Inc, SI5324D-C-GM Datasheet - Page 14

• Manufacturer Part Number: SI5324D-C-GM
• Description: IC CLOCK MULT 2KHZ-150MHZ 36VQFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5324D-C-GM

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 36-VQFN
• Frequency-max: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5324
14
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5324 Register Map.
8, 31, 20,
5, 10, 32
Pin #
19
11
15
16
17
12
13
18
7
6
Pin Name
CKIN1+
CKIN1–
CKIN2+
CKIN2–
RATE0
RATE1
GND
LOL
V
XB
XA
DD
GND
V
I/O
O
DD
I
I
I
I
Signal Level
LVCMOS
3-Level
Supply
Analog
Supply
Multi
Multi
Supply.
The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass capac-
itors should be associated with the following Vdd pins:
5
10
32
A 1.0 µF should also be placed as close to the device as is practical.
External Crystal or Reference Clock.
External crystal should be connected to these pins to use internal
oscillator based reference. Refer to Family Reference Manual for
interfacing to an external reference. External reference must be
from a high-quality clock source (TCXO, OCXO). Frequency of crys-
tal or external clock is set by RATE[1:0] pins.
Ground.
Must be connected to system ground. Minimize the ground path
impedance for optimal performance of this device. Grounding these
pins does not eliminate the requirement to ground the GND PAD on
the bottom of the package.
External Crystal or Reference Clock Rate.
Three level inputs that select the type and rate of external crystal or
reference clock to be applied to the XA/XB port. Refer to the Family
Reference Manual for settings. These pins have both a weak pull-up
and a weak pull-down; they default to M.
L setting corresponds to ground.
M setting corresponds to V
H setting corresponds to V
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
Clock Input 1.
Differential input clock. This input can also be driven with a single-
ended signal. Input frequency range is 2 kHz to 710 MHz.
Clock Input 2.
Differential input clock. This input can also be driven with a single-
ended signal. Input frequency range is 2 kHz to 710 MHz.
PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock indicator if the
LOL_PIN register bit is set to 1.
0 = PLL locked.
1 = PLL unlocked.
If LOL_PIN = 0, this pin will tristate. Active polarity is controlled by
the LOL_POL bit. The PLL lock status will always be reflected in the
LOL_INT read only register bit.
Preliminary Rev. 0.3
0.1 µF
0.1 µF
0.1 µF
DD
DD
Description
.
/2.