SI5367A-C-GQ Silicon Laboratories Inc, SI5367A-C-GQ Datasheet - Page 11

• Manufacturer Part Number: SI5367A-C-GQ
• Description: IC CLOCK MULTIPLIER PROG 100TQFP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5367A-C-GQ

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map.
GND PAD
Pin #
71
77
78
82
83
87
88
90
92
93
97
98
CKOUT3+
CKOUT3–
CKOUT1–
CKOUT1+
CKOUT5–
CKOUT5+
CKOUT2+
CKOUT2–
CKOUT4–
CKOUT4+
Pin Name
GND PAD
CMODE
SDI
Table 3. Si5367 Pin Descriptions (Continued)
GND
I/O
O
O
O
O
O
I
I
Signal Level
LVCMOS
LVCMOS
Supply
MULTI
MULTI
MULTI
MULTI
MULTI
Preliminary Rev. 0.4
Serial Data In.
In SPI microprocessor control mode (CMODE = 1), this
pin functions as the serial data input.
In I
pin is ignored.
This pin has a weak pull-down.
Clock Output 3.
Differential clock output. Output signal format is selected
by SFOUT3_REG register bits. Output is differential for
LVPECL, LVDS, and CML compatible modes. For CMOS
format, both output pins drive identical single-ended
clock outputs.
Clock Output 1.
Differential clock output. Output signal format is selected
by SFOUT1_REG register bits. Output is differential for
LVPECL, LVDS, and CML compatible modes. For CMOS
format, both output pins drive identical single-ended
clock outputs.
Clock Output 5.
Differential clock output. Output signal format is selected
by SFOUT5_REG register bits. Output is differential for
LVPECL, LVDS, and CML compatible modes. For CMOS
format, both output pins drive identical single-ended
clock outputs.
Control Mode.
Selects I
0 = I
1 = SPI Control Mode.
This pin must be tied high or low.
Clock Output 2.
Differential clock output. Output signal format is selected
by SFOUT2_REG register bits. Output is differential for
LVPECL, LVDS, and CML compatible modes. For CMOS
format, both output pins drive identical single-ended
clock outputs.
Clock Output 4.
Differential clock output. Output signal format is selected
by SFOUT4_REG register bits. Output is differential for
LVPECL, LVDS, and CML compatible modes. For CMOS
format, both output pins drive identical single-ended
clock outputs.
Ground Pad.
The ground pad must provide a low thermal and electri-
cal impedance to a ground plane.
2
C microprocessor control mode (CMODE = 0), this
2
C Control Mode.
2
C or SPI control mode for the device.
Description
Si5367
11