SI5324B-C-GMR Silicon Laboratories Inc, SI5324B-C-GMR Datasheet
SI5324B-C-GMR
Specifications of SI5324B-C-GMR
Related parts for SI5324B-C-GMR
SI5324B-C-GMR Summary of contents
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Features Generates any frequency from 2 kHz to 945 MHz and select frequencies to 1.4 GHz from an input frequency of 2 kHz to 710 MHz Ultra-low jitter clock outputs as low as 290 fs rms (12 kHz–20 ...
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Si5324 Functional Block Diagram ÷ N31 CKIN1 CKIN2 ÷ N32 Xtal/Refclock Loss of Signal/ Frequency Offset Signal Detect Loss of Lock 2 Xtal or Refclock ® DSPLL ÷ N1_HS ÷ N2 Control 2 Clock Select I C/SPI Port Device Interrupt ...
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T C ABLE O F ONTENTS Section 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Si5324 1. Electrical Specifications Table 1. Performance Specifications (V = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol Temperature Range T A Supply Voltage V DD Supply Current I DD Input Clock Frequency CK F (CKIN1, ...
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Table 1. Performance Specifications (Continued 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol Output Clocks (CKOUT1, CKOUT2) Common Mode V OCM Differential Output Swing V OD Single Ended Output V SE Swing Rise/Fall Time ...
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Si5324 Table 2. Absolute Maximum Ratings Parameter DC Supply Voltage LVCMOS Input Voltage CKINn Voltage Level Limits XA/XB Voltage Level Limits Operating Junction Temperature Storage Temperature Range ESD HBM Tolerance (100 pF, 1.5 k); All pins except CKIN+/CKIN– ESD MM ...
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Typical Phase Noise Performance Jitter Bandwidth MHz Note: Number of samples: 8.91E9 Figure 1. Broadcast Video Jitter (peak-peak) 5.24 ps Preliminary Rev. 0.3 Si5324 Jitter (RMS) 484 7 ...
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Si5324 Note: Phase noise plot uses brick wall integration. Jitter Bandwidth SONET_OC48, 12 kHz to 20 MHz SONET_OC192_A, 20 kHz to 80 MHz SONET_OC192_B, 4 MHz to 80 MHz SONET_OC192_C, 50 kHz to 80 MHz Brick Wall_800 ...
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Figure 3. Wireless Base Station Phase Noise Jitter Bandwidth Jitter (peak-peak MHz Note: Number of samples: 8.91E9 Preliminary Rev. 0.3 Jitter (RMS) 7.28 ps 581 Si5324 9 ...
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Si5324 130 82 Input Clock Sources* 130 82 Option 1: Crystal V Crystal/Ref Clk Rate Option 2: Refclk+ Refclk– Control Mode (L) Reset Figure 4. Si5324 ...
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Functional Description ÷ N31 CKIN1 CKIN2 ÷ N32 Xtal/Refclock Loss of Signal/ Frequency Offset Signal Detect Loss of Lock Figure 6. Si5324 Functional Block Diagram The Si5324 is a low loop bandwidth, jitter-attenuating clock multiplier for high performance applications. ...
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Si5324 The Si5324 has two differential clock outputs. The signal format of each clock output is independently programmable to support LVPECL, LVDS, CML, or CMOS loads. When configured for CMOS, four clock outputs are available. If not required, the second ...
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Pin Descriptions: Si5324 INT_C1B Pin # Pin Name I/O Signal Level 1 I LVCMOS RST 2, 9, 14 INT_C1B O LVCMOS 4 C2B O LVCMOS Note: Internal register names are indicated by underlined italics, e.g., ...
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Si5324 Pin # Pin Name I/O Signal Level 5, 10 Supply Analog 31, 20, GND Supply GND 19 11 RATE0 I 3-Level 15 RATE1 16 CKIN1+ I Multi 17 ...
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Pin # Pin Name I/O Signal Level 21 CS_CA I/O LVCMOS 22 SCL I LVCMOS 23 SDA_SDO I/O LVCMOS LVCMOS A2_SS I LVCMOS 27 SDI I LVCMOS Note: Internal register names are indicated by ...
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Si5324 Pin # Pin Name I/O Signal Level 29 CKOUT1– O Multi 28 CKOUT1+ 34 CKOUT2– O Multi 35 CKOUT2+ 36 CMODE I LVCMOS GND PAD GND GND Supply Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. ...
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Register Map All register bits that are not defined in this map should always be written with the specified Reset Values. The writing to these bits of values other than the specified Reset Values may result in undefined device ...
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Si5324 Register 128 129 130 DIGHOLD- VALID 131 132 134 135 PARTNUM_RO[3:0] 136 RST_REG ICAL 137 138 139 LOS2_EN[0:0] LOS1_EN[0:0] 142 143 185 Table 3. CKOUT_ALWAYS_ON and SQ_ICAL Truth Table CKOUT_ALWAYS_ON ...
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Register Descriptions Register 0. Bit D7 D6 Name FREE_RUN CKOUT_ ALWAYS_ON Type R R/W R/W Reset value = 0001 0100 Bit Name 7 Reserved Reserved. 6 FREE_RUN Free Run. Internal to the device, route XA/XB to CKIN2. This allows ...
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Si5324 Register 1. Bit D7 D6 Name Reserved Type R Reset value = 1110 0100 Bit Name 7:4 Reserved Reserved. 3:2 CK_PRIOR2 CK_PRIOR 2. [1:0] Selects which of the input clocks will be 2nd priority in the autoselection state machine. ...
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Register 3. Bit D7 D6 Name CKSEL_REG [1:0] Type R/W Reset value = 0000 0101 Bit Name 7:6 CKSEL_REG CKSEL_REG. [1:0] If the device is operating in register-based manual clock selection mode (AUTOSEL_REG = 00), and CKSEL_PIN = 0, then ...
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Si5324 Register 4. Bit D7 D6 Name AUTOSEL_REG [1:0] Type R/W Reset value = 0001 0010 Bit Name 7:6 AUTOSEL_ AUTOSEL_REG [1:0] REG [1:0] Selects method of input clock selection to be used. 00: Manual (either register or pin controlled, ...
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Register 6. Bit D7 D6 Name Reserved SLEEP Type R R/W Reset value = 0010 1101 Bit Name 7 Reserved Reserved. 6 SLEEP SLEEP. In sleep mode, all clock outputs are disabled and the maximum amount of internal cir- cuitry ...
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Si5324 Register 7. Bit D7 D6 Name Type Reset value = 0010 1010 Bit Name 7:3 Reserved. Reserved. 2:0 FOSREFSEL FOSREFSEL [2:0]. [2:0] Selects which input clock is used as the reference frequency for Frequency Off-Set (FOS) alarms. 000: XA/XB ...
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Register 8. Bit D7 D6 Name HLOG_2[1:0] Type R/W Reset value = 0000 0000 Bit Name 7:6 HLOG_2 [1:0] HLOG_2 [1:0]. 00: Normal operation 01: Holds CKOUT2 output at static logic 0. Entrance and exit from this state will occur ...
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Si5324 Register 10. Bit D7 D6 Name Reserved Type R Reset value = 0000 0000 Bit Name 7:4 Reserved Reserved. 3 DSBL2_REG DSBL2_REG. This bit controls the powerdown of the CKOUT2 output buffer. If disable mode is selected, the NC2 ...
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Register 19. Bit D7 D6 Name FOS_EN FOS_THR [1:0] Type R/W R/W Reset value = 0010 1100 Bit Name 7 FOS_EN FOS_EN. Frequency Offset Enable globally disables FOS. See the individual FOS enables (FOSx_EN, register 139). 0: FOS disable 1: ...
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Si5324 Register 20. Bit Name Reserved Type R Reset value = 0011 1110 Bit Name 7:4 Reserved Reserved. 3 CK2_BAD_PIN CK2_BAD_PIN. The CK2_BAD status can be reflected on the C2B output pin. 0: C2B output pin tristated ...
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Register 21. Bit D7 D6 Name Type R R Reset value = 1111 1111 Bit Name 7:2 Reserved Reserved. 1 CK1_ACTV_PIN CK1_ACTV_PIN. The CK1_ACTV_REG status bit can be reflected to the CS_CA output pin using the CK1_ACTV_PIN enable function. CK1_ACTV_PIN ...
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Si5324 Register 22. Bit Name Reserved Type R Reset value = 1101 1111 Bit Name 7:4 Reserved Reserved. 3 CK_ACTV_ POL CK_ACTV_POL. Sets the active polarity for the CS_CA signals when reflected on an output pin. 0: ...
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Register 23. Bit Name Reserved Type R Reset value = 0001 1111 Bit Name 7:3 Reserved Reserved. 2 LOS2_MSK LOS2_MSK. Determines if a LOS on CKIN2 (LOS2_FLG) is used in the generation of an interrupt. Writes to ...
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Si5324 Register 24. Bit D7 D6 Name Reserved Type Reset value = 0011 1111 Bit Name 7:3 Reserved Reserved. 2 FOS2_MSK FOS2_MSK. Determines if the FOS2_FLG is used to in the generation of an interrupt. Writes to this register do ...
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Register 25. Bit D7 D6 Name N1_HS [2:0] Type R/W Reset value = 0010 0000 Bit Name 7:5 N1_HS [2:0] N1_HS [2:0]. Sets value for N1 high speed divider which drives NCn_LS ( low-speed divider. 000: ...
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Si5324 Register 32. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:0 NC1_LS NC1_LS [15:8]. [15:8] Sets value for NC1 low-speed divider, which drives CKOUT1 output. Must odd. 00000000000000000000 = 1 00000000000000000001 = ...
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Register 34. Bit D7 D6 Name Reserved Type R Reset value = 0000 0000 Bit Name 7:4 Reserved Reserved. 3:0 NC2_LS NC2_LS [19:16]. [19:16] Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must odd. 00000000000000000000=1 ...
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Si5324 Register 36. Bit D7 D6 Name Type Reset value = 0011 0001 Bit Name 7:0 NC2_LS [7:0] NC2_LS [7:0]. Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must odd. 00000000000000000000 = 1 00000000000000000001 = ...
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Register 40. Bit D7 D6 Name N2_HS [2:0] Type R/W Reset value = 1100 0000 Bit Name 7:5 N2_HS [2:0] N2_HS [2:0]. Sets value for N2 high speed divider which drives N2LS low-speed divider. 000: 4 001: 5 010: 6 ...
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Si5324 Register 41. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:0 N2_LS [15:8] N2_LS [15:8]. Sets value for N2 low-speed divider, which drives phase detector. 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... ...
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Register 43. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:3 Reserved Reserved. 2:0 N31 [18:16] N31 [18:16]. Sets value for input divider for CKIN1. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 ...
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Si5324 Register 45. Bit D7 D6 Name Type Reset value = 0000 1001 Bit Name 7:0 N31_[7:0 N31_[7:0]. Sets value for input divider for CKIN1. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2 Valid divider ...
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Register 47. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:0 N32_[15:8] N32_[15:8]. Sets value for input divider for CKIN1. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2 Valid divider values ...
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Si5324 Register 55. Bit D7 D6 Name Reserved Type R Reset value = 0000 0000 Bit Name 7:6 Reserved Reserved. 5:3 CLKIN2RATE[2:0] CLKIN2RATE_[2:0]. CKINn frequency selection for FOS alarm monitoring. 000: 10–27 MHz 001: 25–54 MHz 002: 50–105 MHz 003: ...
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Register 128. Bit Name Type Reset value = 0010 0000 Bit Name 7:2 Reserved Reserved. 1 CK2_ACTV_REG CK2_ACTV_REG. Indicates if CKIN2 is currently the active clock for the PLL input. 0: CKIN2 is not the active input ...
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Si5324 Register 130. Bit D7 Name Reserved DIGHOLDVALID Type R Reset value = 0000 0001 Bit Name 6 DIGHOLDVALID Digital Hold Valid. Indicates if the digital hold circuit has enough samples of a valid clock to meet dig- ital hold ...
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Register 131. Bit D7 D6 Name Type Reset value = 0001 1111 Bit Name 7:3 Reserved Reserved. 2 LOS2_FLG CKIN2 Loss-of-Signal Flag. 0: Normal operation. 1: Held version of LOS2_INT. Generates active output interrupt if output interrupt pin is enabled ...
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Si5324 Register 132. Bit D7 D6 Name Reserved Type R Reset value = 0000 0010 Bit Name 7:4, 0 Reserved Reserved. 3 FOS2_FLG CLKIN_2 Frequency Offset Flag. 0: Normal operation. 1: Held version of FOS2_INT. Generates active output interrupt if ...
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Register 134. Bit D7 D6 Name Type Reset value = 0000 0001 Bit Name 7:0 PARTNUM_RO [11:0] Device 2). 0000 0001 1000: Si5324 Others Reserved Register 135. Bit D7 D6 Name PARTNUM_RO [3:0] Type R Reset value ...
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Si5324 Register 136. Bit D7 D6 Name RST_REG ICAL Type R/W R/W Reset value = 0000 0000 Bit Name 7 RST_REG Internal Reset (Same as Pin Reset). Note: The I2C (or SPI) port may not be accessed until 10 ms ...
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Register 137. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:1 Reserved Do not modify. 0 FASTLOCK This bit must be set enable FASTLOCK. This improves initial lock time by dynamically changing the ...
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Si5324 Register 139. Bit Name Reserved LOS2_EN [0:0] Type R R/W Reset value = 1111 1111 Bit Name 7:6, Reserved Reserved. 3:2 5 LOS2_EN [1:0] Enable CKIN2 LOS Monitoring on the Specified Input (2 of 2). Note: ...
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Register 142. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:0 INDEPENDENTSKEW1 [7:0] Register 143. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:0 INDEPENDENTSKEW2 [7:0] INDEPENDENTSKEW2. Register 185. Bit D7 D6 ...
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Si5324 6.1. ICAL The device's registers must be configured for the intended applications. After the part is configured, the part must perform a calibration procedure when there is a stable clock on the selected CLKINn input. The calibration process is ...
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... Ordering Part Output Clock Frequency Number Range Si5324A-C-GM 2 kHz–945 MHz 970–1134 MHz 1.213–1.417 GHz Si5324B-C-GM 2 kHz–808 MHz Si5324C-C-GM 2 kHz–346 MHz Si5324D-C-GM 2 kHz–150 MHz Note: Add the end of the device to denote tape and reel options. Package ...
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Si5324 Any-Frequency Precision Clock Multipliers (Wideband. Bandwidth: 30 kHz to 13 MHz)) Si5322 2 2 Si5325 2 2 Si5365 4 5 Si5367 4 5 Any-Frequency Precision Clock Multipliers w/Jitter Attenuation 8.4 kHz) 2 Si5315 2 ...
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Package Outline: 36-Pin QFN Figure 7 illustrates the package details for the Si5324. Table 6 lists the values for the dimensions shown in the illustration. Figure 7. 36-Pin Quad Flat No-lead (QFN) Symbol Millimeters Min Nom A 0.80 A1 ...
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Si5324 9. Recommended PCB Layout Figure 9. Ground Pad Recommended Layout 56 Figure 8. PCB Land Pattern Diagram Preliminary Rev. 0.3 ...
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Table 7. PCB Land Pattern Dimensions Dimension Notes (General): 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 ...
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Si5324 10. Si5324 Device Top Mark Mark Method: Laser Font Size: 0.80 mm Right-Justified Line 1 Marking: Si5324Q Line 2 Marking: C-GM Line 3 Marking: YYWWRF Line 4 Marking: Pin 1 Identifier XXXX 58 Customer Part Number Q = Speed ...
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Si5324 OCUMENT HANGE IST Revision 0.1 to Revision 0.2 Updated Rise/Fall Time values. Updated minimum loop BW value. Revision 0.2 to Revision 0.25 Updated features and applications. Changed maximum loop bandwidth to 525 ...
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